Multi-threshold Voltage Research Articles

Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed

This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

Multi-threshold voltages in ultra thin-body devices by asymmetric dual-gate structure

Control of threshold voltage (VT) by asymmetric dual-gate structure is investigated. Two separated gates are successfully fabricated through two-step chemical mechanical polishing (CMP) processes. Silicon fin width is determined as same as the thickness of oxide sidewall spacer. VT of the device is modulated by how many charges are trapped in the nitride layer of the second gate stack (G2) through applying programming pulses to G2. They affect the formation of electron channel on the first gate (G1) side. Additionally, the efficiency of this technique is analyzed by simple capacitance network. The thinner body is the more effective the proposed VT control method is. It is noteworthy that this method can be used without ultra thin buried oxide (BOX) structure and additional biasing scheme.

Ion Implantation Applications for Advanced Device Scaling

In the past decade, the surge of mobile devices has been tremendous. These novel mobile devices have all functionalities to communicate as well as gaming, computing capabilities etc. Obviously with such enabling features, mobile devices are a very significant part of the semiconductor market. To address the stringent requirements in terms of battery lifetime, device speed and scaling, the mobile devices processing needed innovations. To achieve these, novel processing techniques in the front end of line (e.g., strained silicon channel, High-K Metal Gate) and novel contact materials for back end of line have been implemented. In addition, the process margin is becoming a key factor as the cost and complexity of making devices is increasing. One dramatic change to address device scalability is the moved to Multigate architecture such as the FinFET (Field Effect Transistor) or GAA (Gate All around Transistors). In fact, the FinFET architecture enables to virtually increase the gate length of the device leading to better electrostatic performance. For FinFET device, due to its three dimension architecture, the junction formation has some unique process requirements. Unlike planar devices, FinFET device requires side wall doping as well as excellent control of junction planarity. In addition, due to the small volume involved with narrow Fin, controlling the Fin damage is becoming a key challenge. To address these, damage engineering for tilted beamline implantation as well as plasma doping approaches have generated great interest. The paper demonstrates the benefits of these novel implantation concepts using different metrologies and device structures. We discuss that these novel implant techniques can also be applied to other applications to further improve FinFET device performances. In order to achieve the multi-threshold voltage (Vth) needed for SoC applications, the work function tuning by implantation is of great interest. Several ideas have been discussed in literature for channel and/or metal gate Vth tuning and are reviewed in this paper. Another key area of interest is the reduction of the device contact resistance. From an implant perspective, several approaches have been reported such as pre-silicide pre-amorphization technique, Schottky Barrier Height (SBH) reduction, or Dopant Segregation Schottky (DSS). We demonstrate that a combination of these contact implant techniques along with advanced annealing provide ways to meet the contact resistance and uniformity need. To further increase channel mobility, new channel materials are being considered to further boost device performance. For PMOS, the move to SiGe or Ge channels is very attractive, however formation of such Fin channels is a challenge. From a diffusion perspective, the main p-type dopant (Boron) has a lower diffusivity as Germanium concentration increases, which may benefit Short Channel Control. However, for NMOS devices, n-type dopants (Arsenic and Phosphorus) diffuse faster than in silicon as well as have lower solubilities. This results in a strong challenge in forming a highly active as well as defect-free junction. We will demonstrate that damage engineering via a combination of novel implant and anneal technologies for junction, damage, and strain will become even more critical for these novel channel materials. Finally we will review the change of architecture to Gate All Around and briefly discuss the multiple implant applications for those new devices.

SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS

Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-Vth) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-Vth devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-Vth devices are desired in the read port for implementing higher performance. However, excessively raised Vth in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.

A Multi-$V_{\mathrm {th}}$ a-IGZO TFT Technology Using Anodization to Selectively Reduce Oxygen Vacancy Concentration in Channel Regions

A multithreshold voltage amorphous indium- gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology based on the anodic oxidation (anodization) technique is demonstrated. It is shown that the characteristics of the a-IGZO channel layer can be considerably tailored by the anodization treatment. As a result, the threshold voltage of the a-IGZO TFTs depends on the anodization voltage, making it possible to fabricate both depletion and enhancement mode TFTs on the same substrate. The secondary ion mass spectrometry result shows that the oxygen content is noticeably increased in the anodized a-IGZO film, suggesting that the dependence of the threshold voltage on the anodization treatment is attributed to the anodization-induced reduction of oxygen vacancy concentration in the channel region, which also leads to an alleviated Vth shift under negative bias illumination stress in the anodized devices.

A design of low swing and multi threshold voltage based low power 12T SRAM cell

This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

A Novel Dual Stack Sleep Technique for Reactivation Noise suppression in MTCMOS circuits

The development of digital integrated circuits is challenged by higher power consumption as low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly hence various high speed ordered multi-threshold voltage CMOS (MTCMOS) circuit techniques are conferred and evaluated during this paper. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, Reactivation noise suppression made throughout the sleep to active mode transitions is a vital challenge in MTCMOS circuits.

Technical Study on Low Power VLSI methods

In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are briefly discussed in this paper. Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate. Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. For a Integrated Circuit (IC) perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII. This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip Index Terms—Logic restructuring, Clock tree and clock Gating, Transistor Sizing, Pin swapping, multi-threshold voltage, Dynamic voltage scaling, DVFS, power gating, Memory splitting, Substrate biasing

Efficient multi‐threshold voltage techniques for minimum leakage current in nanoscale technology

AbstractThe influence of multi‐threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimize the leakage current at lowest value. These algorithms are: Slack Time Search Algorithm (STS), Leakage Power Search Algorithm (LPS), Leakage and Slack Time Search Algorithm (LSS). As a result, 70% of sub‐threshold leakage current is reduced without degrading the performance. Based on 22 nm predictive SPICE parameters proposed by BSIM4, simulation results verified the validity of the proposed algorithms. Copyright © 2010 John Wiley & Sons, Ltd.

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

Multi-Threshold Voltage FinFET Sequential Circuits

New multi threshold voltage (multi-Vth) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-Vth sequential circuits are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage (single-Vth) tied-32 nm-gate FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-Vth tied-gate FinFETs.

Low-Leakage and Compact Registers with Easy-Sleep Mode

Multi-threshold voltage CMOS (MTCMOS) is an effective technique for suppressing the leakage currents in idle circuits. When the conventional MTCMOS technique is directly applied to a sequential circuit however the stored data is lost during the low-leakage sleep mode. Significant energy and timing penalties are suffered to restore the pre-sleep system state at the end of the sleep mode with the conventional MTCMOS circuits. Two new master-slave MTCMOS memory flip-flops are presented in this paper for providing a low-complexity and low-leakage data retention sleep mode. A small size high threshold voltage static memory cell is integrated into an MTCMOS flip-flop to preserve the stored data while drastically reducing the leakage power consumption of idle sequential circuits. The already existing sleep signal of the MTCMOS circuitry is also used for controlling the data retention and restoration operations, thereby eliminating the need for any extra control signals. The memory flip-flops provide a significantly simplified sleep control/data transfer mechanism and reduce the circuit area by up to 37.21% as compared to the previously published MTCMOS flip-flops. Furthermore, the leakage power consumption with the presented techniques is reduced by up to 97.71% as compared to the previously published techniques in a UMC 80 nm CMOS technology.

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

Two new clocking methodologies based on supply voltage and frequency scaling are proposed in this paper for lowering the power consumption and the temperature-fluctuation-induced skew without degrading the clock frequency. The clock signal is distributed globally at a scaled supply voltage with a single clock frequency with the first clocking methodology. Alternatively, dual supply voltages and dual signal frequencies are employed with the second methodology that provides enhanced power savings. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18 ¿m TSMC CMOS technology. Novel multi-threshold voltage level converters and frequency multipliers are employed at the leaves of the clock trees in order to maintain the synchronous system performance. The temperature-fluctuation-induced skew and the power consumption are reduced by up to 80% and 76%, respectively, with the proposed dual supply voltage and dual frequency clock distribution networks as compared to a standard clock tree operating at the nominal supply voltage with a single clock frequency.

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Employing multiple supply voltages (multi- VDD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The new multi-Vth level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.

Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths

This paper addresses the problem of low-power fanout optimization for near-continuous-size inverter libraries. It is demonstrated that because of neglecting short-circuit current, previous techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This paper describes how the problem of low-power fanout optimization can be reduced to inverter-chain optimization problem and formulates the minimization of the total power consumption of an inverter chain as a geometric program. Moreover, it describes an efficient method to minimize the total power consumption of a fanout tree by using multiple-channel-length (multi- L Gate) and multiple-threshold-voltage (multi- Vt) techniques. Experimental results show that the proposed technique can reduce the power consumption of the fanout trees by an average of 11.17% over SIS fanout-optimization program.

Reduced Voltage Scaling in Clock Distribution Networks

We propose a novel circuit technique to generate a reduced voltage swing (RVS) signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV) devices and the programmability of the low voltage value.

Analysis and Efficient Architecture Design for VC-1 Overlap Smoothing and In-Loop Deblocking Filter

In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap smoothing) first and then the vertical edges (for in-loop filtering) or horizontal edges (for overlap smoothing) within a frame, field, or slice. These two filters of VC-1 perform filtering operations on many edges among reconstructed blocks in different processing orders. The entire procedure is very time-consuming and involves high memory access loading for the whole system. This paper analyzes the behavior of VC-1 filters and presents several efficient methods and an integrated architecture design, which involves an overlapped 12times12 block that combines overlap smoothing with in-loop filtering for performance and cost by sharing circuits and system resources. In order to go a step further to efficiently utilize system resources, this paper also presents two other efficient methods, multiple processing order and modified chrominance processing order, which greatly reduce external memory cycles and on-chip memory size for filtered and temporal reconstructed pixels. The specification of the proposed architecture implemented with TSMC 90-nm multithreshold voltage technique has capability to process HDTV1080p 30-fps video and HDTV 2048 t 1536 24-fps video at 200 MHz. The same concept is applicable to other video processing algorithms, especially in deblocking filter for video post-processing in a frame-based order.

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.