A Novel Dual Stack Sleep Technique for Reactivation Noise suppression in MTCMOS circuits

Abstract

The development of digital integrated circuits is challenged by higher power consumption as low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly hence various high speed ordered multi-threshold voltage CMOS (MTCMOS) circuit techniques are conferred and evaluated during this paper. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, Reactivation noise suppression made throughout the sleep to active mode transitions is a vital challenge in MTCMOS circuits.