HIGH PERFORMANCE NOVEL DUAL STACK GATING TECHNIQUE FOR REDUCTION OF GROUND BOUNCE

Abstract

The development of digital integrated circuits is c hallenged by higher power consumption. The combinat ion of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth i n power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to redu ce the leakages in the circuit many low power strategies are identified an d experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EM F of the ground connection we are calling it as ground bounce noise. To reduce this n oise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and i mplementation includes header or footer switch sel ection, sleep transistor distribution choices and sleep transistor gate len gth, width and body bias optimization for area, lea kage and efficiency. Novel dual stack technique is proposed that reduces not only t he leakage power but also dynamic power. The previo us techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed a nd the conditions for the important design parameters (Minimum ground bounce noise) hav e been derived. The Monte-Carlo simulation is perf ormed in Microwind to calculate the values of all the needed parameters f or comparison.