Abstract

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

Highlights

  • CMOS scaling has led to improvement in performance of digital circuits faces significant challenges due to process technology limits

  • In the Static random access memory (SRAM) cell, the output Q depends on bit line (BL) and QB depends on bit line bar (BLB) when write line (WL) is kept high

  • Leakage current and leakage power in independent gate FinFET SRAM cell are shown in Figures 5(a) and 5(b), respectively, in which transient analysis between 0 ns and 100 ns has been done and leakage current is calculated to be approximately equal to 120.3 pA and leakage power becomes 21.46 nW

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Summary

Introduction

CMOS scaling has led to improvement in performance of digital circuits faces significant challenges due to process technology limits. One is the multithreshold leakage reduction technique [7] which uses high threshold PMOS and NMOS acting as a switch to disconnect power supply during standby mode thereby reducing leakage This technique provides increased operating speed by low-threshold MOSFET and reduced leakage by highthreshold voltage. This technique has the disadvantage of increased overall circuit area and introduces extra parasitic capacitance and delay during MOSFET fabrication Another technique is gated-Vdd [8] in which an NMOS transistor with gated voltage supply is connected to the SRAM cell. Stacking effect is produced by additional transistor in combination with the SRAM cell transistors when the gated-Vdd transistor is turned off These techniques have been used to reduce leakage in independent-gate mode of FinFET-based 6T SRAM cell.

Conventional 6T SRAM Cell
FinFET-Based SRAM Cell
Leakage Current Components
Leakage Reduction Techniques
Simulation Results
Conclusion

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