Source of IC power consumption and low power design

Abstract

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.