Mobility In MOSFETs Research Articles

Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel

Although SiGe super-lattice (SL) buried channel was proposed to enhance carrier mobility in MOSFETs, its application on FinFETs is not reported yet. The electrical characteristics of nFinFETs with SiGe and SiGe SL-like buried channels were studied in this letter for the first time. The results show that the electron mobility of nFinFETs with SiGe buried channel is enhanced by an SL-like structure. A higher ON-state current and ON-state/ OFF-state current ratio are also achieved. However, the sub-threshold swing and reliability characteristics need improvement due to slight degradation of interface quality.

Macroscopic simulations of the SiC thermal oxidation process based on the Si and C emission model

The interface defects formed at the oxide–SiC interface impact not only on channel mobility of MOSFET but also on many scenes such as generation or extinction of Si/C atom vacancies and formation of single-photon sources. Therefore, it is very important to know the oxidation mechanism of SiC more in detail. We have previously proposed a unified SiC oxidation model based on the Si and C emission phenomenon. In addition, it has been revealed that this model accurately reproduces the oxide growth rate in the entire oxide thickness range for various oxidation conditions and substrate surface orientations. In this report, based on the experimental verifications for the four oxidation stages deduced from this unified oxidation model, the validity of this model was reviewed. Furthermore, the interface-emitted Si and C concentrations were simulated for various oxidation temperatures and substrate surface orientations. Based on the simulation results together with experimental results of interface state density, the optimum oxide growth condition has been discussed.

Effects of LaSiO<italic>x</italic> Thickness and Forming Gas Anneal Temperature on Threshold Voltage Instability of 4H-SiC MOSFETs With LaSiO<italic>x</italic>

We report the effects of lanthanum-rich layer thickness and forming gas anneal (FGA) conditions on mobility and threshold voltage ( ${V} _{{\text {T}}}$ ) instability of high-mobility 4H-SiC MOSFETs using lanthanum silicate (LaSiO x ) interface engineering. MOSFETs with LaSiO x after high-temperature FGA show significantly improved ${V} _{\text {T}}$ reliability under positive gate bias. It is found that both the thickness of the initial lanthanum-rich layer and the FGA temperature profoundly influence MOSFET mobility and ${V} _{\text {T}}$ instability under positive bias. There is a tradeoff between mobility and ${V} _{\text {T}}$ shift under positive bias.

Investigation of the Universal Mobility of SiC MOSFETs Using Wet Oxide Insulators on Carbon Face With Low Interface State Density

The universal mobility of SiC MOSFETs has been investigated. SiC MOSFETs with the gate oxide formed by wet oxidation have been fabricated on 4H-SiC ( $000\overline {\textsf {1}}$ ) substrates to reduce Coulomb scattering sources. In order to suppress charge trapping in the gate oxide during measurement, surface carrier concentration ( ${N}_{s}$ ), and channel current have been evaluated from the transient characteristic of source current and drain current under the application of pulse gate bias. To eliminate the influence of charge trapping in interface states, the concentration of electrons trapped in interface states has been estimated and subtracted from ${N}_{s}$ . Effective channel mobility ( $\mu _{\textsf {eff}}$ ) and effective electric fields ( ${E}_{\textsf {eff}}$ ) have been calculated from the ${N}_{\textsf {s}}$ and channel current. The substrate impurity concentration ( ${N}_{A}$ ) and substrate bias ( ${V}_{b}$ ) dependence of $\mu _{\textsf {eff}}$ – ${E}_{\textsf {eff}}$ characteristics have been investigated, and, as a result, it has been confirmed that $\mu _{\textsf {eff}}$ of SiC MOSFETs shows a universal characteristic as a function of ${E}_{\textsf {eff}}$ at high ${E}_{\textsf {eff}}$ , independent of ${N}_{\textsf {A}}$ and ${V}_{\textsf {b}}$ . In addition, we have investigated the temperature dependence of this universal mobility in the range of 223–423 K, and formulated the result in a simple model. This result leads to a better understanding of electron transport properties in SiC inversion layers and the improvement of the accuracy of device and circuit simulations of SiC MOSFETs.

High-Mobility SiC MOSFETs Using a Thin-SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> Gate Stack

We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2 interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DIT and channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Theoretical study of strain-induced modulation of the bandgap in SiC

The low electron mobility of 4H-SiC MOSFETs at the (0001) interface is a problem for high-performance power devices, and some experiments have shown higher electron mobilities by using other interfaces. We studied bandgap modulation induced by strain and showed that different bandgap modulations occur in different SiC polytypes. Moreover, we found that biaxial strain causes a larger modulation than hydrostatic strain, and that biaxial strain in the and planes causes a larger modulation than that in the (0001) plane for 4H-SiC. The modulated bandgap acts as electron traps and degrades the electron mobility of 4H-SiC MOSFETs. However, the effects of bandgap modulation appear strongly and the number of electronic states increases in 4H-SiC MOSFETs on the (0001) interface when considering the intrinsic nature of 4H-SiC. Therefore, appropriate interface orientations must be used for high-electron-mobility 4H-SiC MOSFETs.

Carrier Mobility Enhancement by Applying Back-Gate Bias in Ge-on-Insulator MOSFETs

In this letter, we comprehensively study the carriers’ mobility and the effect of back-gate bias ( ${V} _{\textsf {bg}}$ ) in Ge-on-insulator (GeOI) MOSFETs with various working modes, including accumulation mode (AM) nMOSFET, inversion mode (IM) nMOSFET, AM pMOSFET, and IM pMOSFET. The results show that the AM nMOSFETs and pMOSFETs have higher drain currents and carriers’ mobility. The electron mobility increases under positive ${V} _{\textsf {bg}}$ and decreases under negative ${V} _{\textsf {bg}}$ . While the hole mobility has the opposite ${V} _{\textsf {bg}}$ dependence. The carriers’ mobility of AM MOSFETs is proved to benefit more from ${V} _{\textsf {bg}}$ due to the increase of carriers’ densities. The peak mobility enhancements of more than 100% for holes and 35% for electrons are achieved in GeOI MOSFETs by applying ${V} _{\textsf {bg}}$ .

Origin of High Mobility in InSnZnO MOSFETs

The origins of higher mobility characteristics of In-Sn-Zn-O (InSnZnO) MOSFETs than those of conventional In-Ga-Zn-O (InGaZnO) MOSFETs were investigated. Comprehensive analyses of temperature and surface carrier concentration ( ${N} _{s}$ ) dependence of mobility revealed the aspects of potential profile around mobility edge ( ${E} _{c}$ ) in InSnZnO MOSFET. Incorporated Sn atoms were found to increase the potential fluctuation around ${E} _{c}$ at low ${N} _{s}$ compared to conventional InGaZnO MOSFET, but enhance the overlapping of electron orbitals of cations with In atoms, which results in mobility improvement by band transport.

Investigation of nitridation and oxidation reactions at SiC/SiO2 interfaces in NO annealing and modeling of their quantitative impacts on mobility of SiC MOSFETs

Nitridation and oxidation reactions at SiC/SiO2 interfaces during NO annealing were investigated and their quantitative impacts on the channel mobility were modeled. We evaluated the NO annealing condition dependence of nitrogen atom concentration at the SiC/SiO2 interfaces ([N]) and increased oxide thickness (ΔTOX), as indices of the nitridation and oxidation reactions, respectively. By using the obtained [N] and ΔTOX, the experimental mobility was well reproduced in an empirical formula. This empirical formula enables evaluation of the quantitative impact of the nitridation and oxidation reactions on the mobility. From the empirical formula, it was expected that the mobility would be further increased by lowering the annealing temperature from the investigated temperature range. However, an exponential increase in both NO gas consumption and processing time is also predicted, which leads to the conclusion that the further decrease in annealing temperature would be impracticable.

Channel Mobility in GaN Hybrid MOS-HEMT Using SiO2as Gate Insulator

The channel mobility in SiO2/GaN hybrid metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) has been studied. The formalism used for the inversion mobility in MOSFETs has been adapted to the case of GaN MOS-HEMTs, which operate in accumulation condition. Using the values of interface trapped charges ( ${Q}_{{ {\,trap}}} = {1.35} \times {10}^{12}$ cm $^{{ {-2}}}$ ) and surface roughness (RMS = 0.15 nm) determined by capacitance-voltage measurements and nanoscale morphological analyses allowed to derive meaningful physical parameters for the mobility model. The temperature dependence of the peak mobility—that decreases from 110 cm $^{{ {2}}}\text{V}^{ {-1}}\text{s}^{{ {-1}}}$ at room temperature down to 91 cm $^{{ {2}}}\text{V}^{{ {-1}}}\text{s}^{{ {-1}}}$ at 423 K—is mainly ruled by phonon and Coulomb scattering effects. The implications in practical devices were discussed, considering the possible improvement of the device on-resistance that can be obtained by reducing the interfaces state density at the SiO2/GaN interface.

Dependence of electron mobility on gate voltage sweeping width and deposition temperature in MOSFETs with HfO2/Al2O3/InGaAs gate stacks

In this study, we fabricated MOSFETs with Al2O3/InGaAs or HfO2/Al2O3/InGaAs gate stacks. The surface was subjected to nitrogen plasma and trimethylaluminum cleaning prior to low-temperature atomic layer deposition. Electron mobility was extracted using the capacitance–gate voltage (C–VG) and drain current–gate voltage (ID–VG) characteristics. We determined that the mobility decreased when the gate voltage sweeping width increased during C–VG and ID–VG measurements. In addition, we determined that the lowering of the deposition temperature to 120 °C improved the mobility of MOSFETs with HfO2/Al2O3/InGaAs gate stacks as compared with that corresponding to deposition at 300 °C. Furthermore, HfO2/Al2O3/InGaAs gate stacks with various Al2O3 thicknesses were fabricated. When the number of Al2O3 deposition cycles was more than 4, the mobility of MOSFETs with HfO2/Al2O3/InGaAs gate stacks improved, reaching the value of the Al2O3/InGaAs gate stack.

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11nm.

Impact of Sacrificial Cosumption of Substrate By Thermal Oxidation on Electron Mobility of 4H-SiC Mosfets

4H-SiC MOSFETs are extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. A significant degradation of electron mobility in inversion channel has been often reported, however, the dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study we investigated the effects of thermal oxidation during MOSFET fabrication processes on the quality of substrate surface, from the view point of channel mobility degradation. Lateral n-MOSFETs with various gate length, Lg=80~500 μm, were fabricated on p-type 4H-SiC (0001) wafers with Al-doped epitaxial layers. Source/drain (S/D) regions were formed by P implantation, followed by an activation annealing at 1650°C with a carbon cap. Ni Ohmic contacts for n+ S/D were formed by PMA at 1000°C for 1 min in N2 ambient. Finally Al was deposited and patterned as the gate electrode. Before the gate oxide formation, we intentionally consumed 5~60 nm of SiC substrate by a thermal oxidation followed by a chemical etching of SiO2 in HF solution. The gate oxide was thermally-grown in dry-O2 at 1300°C, followed by a post-oxidation-annealing in O2 at 800°C [1]. The consumed SiC thickness in total, including the gate oxide formation process as the final step, was varied from 9 to 72 nm. As a result, a degradation of field-effect-mobility was clearly observed when the sacrificially-consumed SiC thickness increased. To avoid the additional effects of surface damage due to the high-temperature activation annealing, we also prepared a MOSFET without 1650°C annealing, and successfully observed a further enhancement of channel mobility ~10% by minimizing the consumed SiC thickness during the device fabrication processes. Even though we expected the activation of only a few percentage of implanted P atoms, thanks to the thermal oxidation process at 1300oC for this sample, we could extract the channel mobility after the calibration of the effects of the parasitic resistance from Lg-dependence of channel resistance. These results clearly indicate that the sacrificial consumption of SiC substrate surface results in a monotonic degradation of channel mobility. The mechanism of such deterioration has not been clarified yet, but we believe that a degradation of SiC surface quality, possibly due to an accumulation of Al dopants [2] or interstitial C atoms near the SiC surface during the oxidation processes, would explain such change of MOSFET performance.[1] R. H. Kikuchi and Koji Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] T. Kobayashi et al., Appl. Phys. Express 7, 121301 (2014).

Effects of antimony (Sb) on electron trapping near SiO2/4H-SiC interfaces

To investigate the mechanism by which Sb at the SiO2/SiC interface improves the channel mobility of 4H-SiC MOSFETs, 1 MHz capacitance measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on Sb-implanted 4H-SiC MOS capacitors. The measurements reveal a significant concentration of Sb donors near the SiO2/SiC interface. Two Sb donor related CCDLTS peaks corresponding to shallow energy levels in SiC were observed close to the SiO2/SiC interface. Furthermore, CCDLTS measurements show that the same type of near-interface traps found in conventional dry oxide or NO-annealed capacitors are present in the Sb implanted samples. These are O1 traps, suggested to be carbon dimers substituted for O dimers in SiO2, and O2 traps, suggested to be interstitial Si in SiO2. However, electron trapping is reduced by a factor of ∼2 in Sb-implanted samples compared with samples with no Sb, primarily at energy levels within 0.2 eV of the SiC conduction band edge. This trap passivation effect is relatively small compared with the Sb-induced counter-doping effect on the MOSFET channel surface, which results in improved channel transport.

An Improved Surface Roughness Scattering Model for Bulk, Thin-Body, and Quantum-Well MOSFETs

This paper reports about the implementation in a multisubband Monte Carlo device simulator of a comprehensive surface roughness scattering model, based on a nonlinear relation between the scattering matrix elements and the fluctuations Δ(r) of the interface position. The model is first extended by including carrier screening effects and accounting for scattering at multiple interfaces, and it is then used for the analysis of relevant experimental data sets. We show that the new model can reproduce fairly well the silicon universal mobility curves as well as mobility data for ultrathin-body InGaAs MOSFETs using Δ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> values consistent with atomic force microscopy (AFM) and TEM measurements. Our simulation results and some experimental data also indicate that mobility in InGaAs MOSFETs is reduced with decreasing well thickness, T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> , with a weaker dependence compared with the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> behavior observed in Si devices.

Influence of Oxide Processing on the Defects at the SiC-SiO&lt;sub&gt;2&lt;/sub&gt; Interface Measured by Electrically Detected Magnetic Resonance

Anneals in nitrogen (N) containing atmosphere have been proven as efficient means of improving the channel mobility of SiC MOSFETs. It has been demonstrated that simultaneously the density of interface traps is reduced. However, this process is not yet fully understood. In this study we show a comparison of MOSFETs annealed in different atmospheres and compare their electrically detected magnetic resonance (EDMR) spectra with electrical parameters. We find hints for the N incorporation not only passivating but also creating or transforming defects.

Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

The embedded epitaxial silicon germanium (eSi1-xGex) in the recessed source/drain (S/D) area modulates the lattice constant and band structure of silicon at the channel region then enhances the hole/electron mobility of MOSFETs. For the 28nm node planar devices, the strict control of recessed profile could be achieved by plasma-based one-step or two-step silicon dry etch process combined with the post wet chemical treatments. Here we analyzed the process loading correlated to the pitch of gate electrodes and the tunable capability on final sigma-shaped trench profile for these two types of processes. The strain/stress induced mobility enhancement technique of fin structure FETs should be significantly different from that of traditional planar FETs. We successfully decoupled the trade-off between the gate capping layer protection and the silicon nitride spacer pull-back before the p-channel fin recess step. Additionally, by balancing the isotropic and anisotropic spacer open parts in the whole etch process, we also demonstrated the fin structures with flat and smooth recessed surface on their top area, which would benefit for future good crystalline and well controlled Pi-shaped eSi1-xGex growth.

(Invited) Effects of Ge Substrate Annealing in H2 on Electron Mobility as well as on Junction Leakage in n-channel Ge MOSFETs

This paper discusses H2 annealing effect of Ge substrate on carrier mobility and junction leakage current in Ge MOSFETs. We found that H2 annealing of Ge wafer improved the electron mobility in Ge n-channel MOSFETs, while it degrades n+/p junction leakage current. Although we have not clarified the mechanisms causing such significant effects, we have found that the oxygen content in Ge surface region is phenomenologically related to above effects of Ge in H2 annealing.

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

Critical issues for high quality Ge/III-V MOS gate stacks have been reviewed and discussed. For Ge gate stacks, a plasma post oxidation method can realize high quality ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks. We have evaluated limiting factors of electron and hole mobility in Ge MOSFETs. The Ge MOS channel mobility in a high Ns region is significantly degraded by surface roughness scattering as well as trapping of free carriers into interface states inside the Ge bands. It is shown that reduction in surface roughness through low temperature PPO and reduction in Dit inside the bands due to atomic Deuterium annealing can improve the effective mobility in the high Ns region. For InGaAs gate stacks, ALD La2O3 gate stacks yield lower Dit than the Al2O3 ones. For GaSb gate stacks, high ALD temperature or annealing temperature increases Dit at Al2O3/GaSb interfaces. InAs passivation for GaSb surfaces can effectively significantly improve the MOS interface properties and the thermal stability of the Al2O3/GaSb interfaces.

Transient-Current Method for Measurement of Active Near-Interface Oxide Traps in 4H-SiC MOS Capacitors and MOSFETs

Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method.