Abstract
Critical issues for high quality Ge/III-V MOS gate stacks have been reviewed and discussed. For Ge gate stacks, a plasma post oxidation method can realize high quality ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks. We have evaluated limiting factors of electron and hole mobility in Ge MOSFETs. The Ge MOS channel mobility in a high Ns region is significantly degraded by surface roughness scattering as well as trapping of free carriers into interface states inside the Ge bands. It is shown that reduction in surface roughness through low temperature PPO and reduction in Dit inside the bands due to atomic Deuterium annealing can improve the effective mobility in the high Ns region. For InGaAs gate stacks, ALD La2O3 gate stacks yield lower Dit than the Al2O3 ones. For GaSb gate stacks, high ALD temperature or annealing temperature increases Dit at Al2O3/GaSb interfaces. InAs passivation for GaSb surfaces can effectively significantly improve the MOS interface properties and the thermal stability of the Al2O3/GaSb interfaces.
Published Version
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