(Invited) Border-Trap Characterization for Ge Gate Stacks with Thin GeOX layer Using Deep-Level Transient Spectroscopy

Abstract

1) Introduction Ge is one of the candidate materials for the future high performance MOSFET. In order to embody the high performance Ge-MOSFET, stacked gate dielectrics with thin Ge oxide interlayer, such as SiO2/GeO2 and Al2O3/GeOx, have been studied actively [1, 2]. On the other hand, in the case of Ge-MOS gate stacks, not only interface traps (ITs) but border traps (BTs) located in gate dielectric are also problematic because they degrade MOS characteristics and mobility of the MOSFET. For deep understanding and performance improvement of Ge MOS gate stacks, both density and position of BT in stacked gate dielectrics should be clarified. However, in-depth study of BT in Ge gate stacks is limited.Recently, we succeeded in separating the BT and IT signals using deep-level transient spectroscopy (DLTS) in SiO2/GeO2/Ge gate stacks grown by thermal and plasma oxidation [3,4].In this study, the densities of IT (D it) and BT (N bt) in Al2O3/GeOx/p-Ge gate stacks grown by post plasma oxidation (PPO) were evaluated. In addition, to study the relationship between BTs and mobility of devices, Ge p-MOSFETs with Al2O3/GeOx/Ge gate stacks were also fabricated and characterized. The effect of BTs on the mobility of MOSFETs is also discussed. 2) Experimental P-type (100) Ge substrate with a doping concentration of 2.3×1016 cm-3 was used. After chemical cleaning by HF solution, the first layer of Al2O3 was deposited at 300°C by ALD with precursors of water and trimethylaluminum for 3, 9, 14 and 20 cycles, corresponding to four samples, followed by PPO using electron cyclotron resonance (ECR) at room temperature. The GeOx thicknesses in Al2O3 gate stacks with 3, 9, 14 and 20 ALD cycles were 0.87, 0.42, 0.06, and 0.16 nm, respectively. The second layer of Al2O3 was deposited at 300°C by ALD for 25 cycles to avoid current leakage during electrical measurements. A 400°C post-deposition annealing for 30 min was performed. Then, the TiN layer was deposited by sputtering, followed by 350°C post-metallization annealing for 20 min. After that, the Al layer was also deposited and gate electrode was patterned. To improve the electrical contact between TiN and Al layers, a contact annealing was performed at 300°C for 10 min. Finally, an InGa back contact was formed.Ge p-MOSFETs were fabricated on n-type (100) Ge substrate with a doping concentration of 9.3 × 1015 cm-3. We used a gate-first process. An Al2O3/GeOx/Ge gate stack was fabricated by the same method as MOS capacitors as mentioned above. The source/drain (S/D) region was fabricated using B ion implantation, followed by the activation annealing (for S/D) at 300°C for 10 min. The active hole density of 4.3×1019 cm-3 was confirmed by Hall Effect measurement. 3) Summary of the r esults ITs and BTs in Al2O3/GeOx/p-Ge gate stacks were characterized using DLTS. Through evaluating the gate stacks with different GeOx thickness, the respective BTs in Al2O3, Al2O3/GeOx interface region, and GeOx were successfully detected. The D it near to mid-gap is lower in the MOS capacitors with a thicker GeOx, while the D it near to valence band is lower in the MOS capacitor with a thinner GeOx, which is probably due to the defect termination by Al oxide. The N bt in Al2O3 was 6~9×1017 cm-3, which is lower than those in GeOx (~2×1018 cm-3), and the highest N bt of ~1×1019 cm-3 was found in Al2O3/GeOx interface region.Ge p-MOSFETs with Al2O3/GeOx/p-Ge gate stacks were analyzed. It was confirmed that the ITs and the BTs near to valence band edge of Ge affect the effective mobility of Ge p-MOSFETs in high field region. Therefore, reduction of ITs and BTs near to valence band is the key to reach high-performance p-MOSFETs. In this sense, Al2O3 is a suitable dielectric material for Ge p-MOSFETs. Acknowledgement This work was partially supported by (JSPS) KAKENHI (grant numbers 17H03237 and 18KK0134) and Advanced Graduate Program in Global Strategy for Green Asia, Kyushu University.