Low Drain Voltage Research Articles

High-Efficiency Low Voltage Inverse Class-F Power Amplifier Design Based on Harmonic Control Network Analysis

A high-efficiency inverse Class-F (Class-F−1) power amplifier (PA) with a low voltage pHEMT is presented in this paper. The design process is based on a novel harmonic control network (HCN), consisting of a bias circuit (BC) and a low pass filter (LPF). The goal is reducing the impact of fundamental frequency reflection on DC supply, elimination of harmonics, improvement of power added efficiency (PAE), shaping the voltage and current waveforms along with enhancing the performance of the PA. The simulation is performed based on the harmonic balance analysis in order of 9. The implemented Class-F−1 PA is simulated and measured at 2.4 GHz. The maximum measured PAE of 76% and the drain efficiency of 82% are achieved, with a low drain voltage of 3 V and 11.2 dB gain under a 16 dBm input power. The proposed PA is fabricated and measurement results validated the simulations.

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Modeling of contact resistance effect on low frequency noise in indium–zinc oxide thin-film transistors

Low frequency noise in the indium–zinc oxide thin-film transistors (IZO TFTs) at low drain voltage is investigated in this paper. First, the contact resistance is extracted from transfer characteristics. By analyzing the noise behavior under different bias conditions, the measured noises in IZO TFTs have been separated into contributions from the channel and contacts. Determined by the channel and the contact, the normalized noise varied with two slopes ([Formula: see text] and 2) with the increment of effective gate voltage. Moreover, the values of flat-band voltage noise spectral density and Coulomb scattering parameter have been extracted. By considering contact resistance, the normalized noise has also been modeled by the use of carrier number with the correlated mobility fluctuation [Formula: see text] model.

Two dimensional Green's function solution of threshold for junction less field effect transistors at low drain voltage

The threshold voltage is an important device and circuit parameter of any FET structure. In this paper, closed form analytic expressions are derived which determine the dependence of the threshold voltage of DGJLFETs on device dimensions, and the drain voltage. The depletion approximation and the two dimensional Green's function are used to determine the terminal behavior of the device. The model includes the effect of the depletion in the gate-drain spacing. The threshold condition is reached when the depletion layers from the two sides cross i.e., when the channel pinches off. The widening of the depletion layer under sub-threshold condition, and the movement of the pinch-off point with the drain voltage are calculated. Finally, the shift in threshold voltage and DIBL with the gate length is determined. We can also determine the potential distribution within the device. To verify our calculations, the analytical results are compared with 2-D numerical simulations. The agreement is especially good at low drain voltages.

Nanoprinted Quantum Dot–Graphene Photodetectors

AbstractPhotodetectors utilizing graphene field‐effect transistors sensitized by colloidal quantum dots exhibit high responsivities under infrared light illumination. Precise, microscopic spatial control over quantum dot deposition is required to gain deeper insight into device mechanisms, optimize device performance, and enable new device architectures and applications. The latter may eventually include photodetectors with subwavelength device dimensions. Here, infrared photodetectors are fabricated by electrohydrodynamic nanoprinting of colloidal PbS quantum dots onto graphene field‐effect transistors with varying quantum dot layer thicknesses on a single substrate, demonstrating the potential of the method for realizing small footprint detectors with high spatial resolution. Remarkably, while the responsivity of the photodetectors increases with increasing layer thicknesses up to 130 nm, the noise current is found to be independent of the layer thickness. In addition, the responsivity and noise current are both linearly dependent on the applied drain voltage and drain current. As a result, the specific detectivity is independent of the drain voltage, and the detector can be operated at lower drain voltages thus reducing power consumption. Finally, specific detectivities of at least 109 Jones at 1200 nm are obtained, without degradation of the charge carrier mobilities in graphene from the electrohydrodynamic printing.

Enhanced Charge Injection Properties of Organic Field-Effect Transistor by Molecular Implantation Doping.

Organic semiconductors (OSCs) have been widely studied due to their merits such as mechanical flexibility, solution processability, and large-area fabrication. However, OSC devices still have to overcome contact resistance issues for better performances. Because of the Schottky contact at the metal-OSC interfaces, a non-ideal transfer curve feature often appears in the low-drain voltage region. To improve the contact properties of OSCs, there have been several methods reported, including interface treatment by self-assembled monolayers and introducing charge injection layers. Here, a selective contact doping of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4 -TCNQ) by solid-state diffusion in poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT) to enhance carrier injection in bottom-gate PBTTT organic field-effect transistors (OFETs) is demonstrated. Furthermore, the effect of post-doping treatment on diffusion of F4 -TCNQ molecules in order to improve the device stability is investigated. In addition, the application of the doping technique to the low-voltage operation of PBTTT OFETs with high-k gate dielectrics demonstrated a potential for designing scalable and low-power organic devices by utilizing doping of conjugated polymers.

Novel attributes of bandstructure effect on the performance of germanium Schottky barrier MOSFET

A detailed study of the bandstructure effect on the performance of a double-gate germanium Schottky barrier MOSFET (Ge-SBFET) is investigated. An accurate calculation of the thickness-dependent 2D bandstructure is employed within a 20 orbital sp3d5s* tight-binding formalism, and the quantum transport of the carriers is elucidated based on the non-equilibrium Green’s function formalism. Quantum confinement considerably changes the bandstructure profile of the Ge-SBFET and causes the energy difference of the valleys to rearrange. For a channel thickness of about 1.5 nm, the two-fold X2 type valleys with major axes at the point form a subband with minimum energy, and the energy split is reduced to 13 meV, which compensates for the lack of density of states in the nanoscale regime. Moreover, the strong transverse confinement of the ultra-thin body Ge-SBFET increases the effective Schottky barrier height and a parabolic potential profile with discrete resonant states is formed along the current transport direction, mainly at low drain voltages. Resonant tunnelling creates oscillations in the transfer characteristic, especially at low temperatures and at a reduced value of drain voltages. The impact of the physical and structural parameters, which may affect the resonant tunnelling in a Ge-SBFET, is thoroughly analysed. The results in this paper pave the way towards elucidating the applications of nanoscale Ge-SBFETs.

Body Effects on the Tuning RF Performance of PD SOI Technology Using Four-Port Network

For partially depleted (PD) silicon-on-insulator (SOI) technology, body contact technology, such as T-gate (TB) body contact, is often used to suppress the floating body effect for analog or radio frequency (RF) circuits. RF performance is usually measured using a two-port network with body node connected to source node, thereby limiting the potential applications of PD SOI technology. In this letter, a four-port network structure was used for TB SOI MOSFET to evaluate the influence of the body potential on the RF performance. The gate to source and body capacitance were also extracted, individually. It was found that TB device can have an 89% improvement in the cut-off frequency ( ${f}_{T}$ ) by tuning the body voltage to 0.5 V when the device was operated at gate voltage equals to 0.4 V and drain voltage equals to 0.3 V. Power dissipation reduction was also observed with forward body bias and lower drain voltage. The results indicate that four-port network structure has potential in RF modeling for PD SOI technology that could facilitate integrating the PD SOI process into low power applications.

In situ transmission electron microscopy of transistor operation and failure

Microscopy is typically used as a post-mortem analytical tool in performance and reliability studies on nanoscale materials and devices. In this study, we demonstrate real time microscopy of the operation and failure of AlGaN/GaN high electron mobility transistors inside the transmission electron microscope. Loading until failure was performed on the electron transparent transistors to visualize the failure mechanisms caused by self-heating. At lower drain voltages, thermo-mechanical stresses induce irreversible microstructural deformation, mostly along the AlGaN/GaN interface, to initiate the damage process. At higher biasing, the self-heating deteriorates the gate and catastrophic failure takes place through metal/semiconductor inter-diffusion and/or buffer layer breakdown. This study indicates that the current trend of recreating the events, from damage nucleation to catastrophic failure, can be replaced by in situ microscopy for a quick and accurate account of the failure mechanisms.

The effects of the peaking currents on the performance of the Doherty power amplifier: an analytical and experimental study

Recognizing that the ratio of the peaking and main amplifier transconductances is a crucial parameter in the design of Doherty power amplifiers, we propose an analytical method to specify the optimum value of this ratio. The method is validated both through simulations based on circuit-level model of the Doherty power amplifier and the experiments using a 100 W dual driven symmetrical LDMOS Doherty power amplifier manufactured. According to the experiments, overdriven peaking amplifier is resulting in lower drain voltage at the main side, hence causing low power efficiency. Conversely, underdriven peaking amplifier is saturating the main amplifier, which in turn results in decreased linearity. Both simulation and experimental results clearly revealed that the amplifier efficiency and linearity strongly depend on the drive levels of the main and peaking amplifiers. The third-order intermodulation distortion of a 44 dBm and 2.655 GHz Doherty power amplifier which is measured as − 29.75 dBc in the overdriven case, is increased up to − 19.40 dBc in the underdriven case. However, the drain efficiency which is measured at 47.84% in the overdriven case is improved to 54.36% when the peaking amplifier is operated in the underdriven mode for 47 dBm and 2.655 GHz.

Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance.

Low voltage operation of GaN vertical nanowire MOSFET

GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10−14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66–122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application.

Experimental investigation on On–Off current ratio behavior near onset voltage for a pentacene based organic thin film transistor

The performance of a pentacene based organic thin film transistor (OTFT) with polymethylmethacrylate as a dielectric insulator and indium tin oxide based electrical gate is investigated. On the one hand, we showed that the threshold voltage increases with gate voltage, and on the other hand that it decreases with drain voltage. Thus, we noticed that the onset voltage shifts toward positive voltage values with the drain voltage increase. In addition, threshold-onset differential voltage (TODV) is proposed as an original approach to estimate an averaged carrier density in pentacene. Indeed, a value of about 4.5 × 1016 cm−3 is reached at relatively high gate voltage of −50 V; this value is in good agreement with that reported in literature with other technique measurements. However, at a low applied gate voltage, the averaged pentacene carrier density remains two orders of magnitude lower; it is of about 2.8 × 1014 cm−3 and remains similar to that obtained from space charge limited current approach for low applied bias voltage of about 2.2 × 1014 cm−3. Furthermore, high IOn/IOff and IOn/IOnset current ratios of 5 × 106 and 7.5 × 107 are reported for lower drain voltage, respectively. The investigated OTFTs also showed good electrical performance including carrier mobility increasing with gate voltage; mobility values of 4.5 × 10−2 cm2 V−1 s−1 and of 4.25 × 10−2 cm2 V−1 s−1 are reached for linear and saturation regimes, respectively. These results remain enough interesting since current modulation ratio exceeds a value of 107 that is a quite important requirement than high mobility for some particular logic gate applications.

Current oscillations in Schottky-barrier CNTFET: towards resonant tunneling device operation

In this work, it has been shown that current oscillations could be enhanced in Schottky-barrier carbon nanotube FET (SB-CNFET) particularly at the low drain voltage and small channel lengths. This oscillatory dependence on the gate voltage brings out negative differential transconductance regions. We have simulated the SB-CNTFET using a 2D quantum simulator by solving NEGF and Poisson’s equation self-consistently. A parabolic potential well profile between double barriers is formed along the transport direction of the channel which is responsible for these oscillations. Key factors that affect the current oscillations are thoroughly investigated such as drain voltage, channel length, CNT diameter, the dielectric constant of the gate oxide and temperature. The results of this work pave a way to shed light on the feasibility and enhancement of SB-CNTFET as a resonant tunneling device.

A novel method for reduction of leakage current in MOSFET

In this paper, structural modification of conventional bulk MOSFET has been proposed for minimisation of subthreshold leakage current. Key structural features of bulk MOSFET have been kept unaltered. Comparison of conventional and proposed structure has been presented for a 20 nm NMOS with 0.8 volt Vdd. The proposed structure is capable of reducing subthreshold leakage current even at very low drain voltage when the gate voltage is zero. Around 55% reduction of OFF current has been obtained when drain voltage is at Vdd and gate voltage is zero. The methodology proposed does not have any special requirement at the circuit level, and can be combined with all circuit level methodologies. The proposed structure is named as 'defensive MOSFET' as it looks like a defensive shield. Structural dimensions of 20 nm MOSFET generation have been taken from the 2011 edition of International Technology Roadmap for Semiconductors or ITRS. All simulation processes have been executed by Sentaurus G-2012.06 Technology Computer Aided Design or TCAD software.

P-Channel and N-Channel Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Ultralow Power CMOS

In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.

Study of HCI Reliability for PLDMOS

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.

Heavily-Doped SOI with SAM-Based Gate Dielectrics in Application to TMDC FETs

Semiconducting transition metal dichalcogenides (TMDC) have been growing interest for both scientific interest and practical applications because of their various material properties. Potential applications and fundamental understanding in new classes of semiconductor materials motivates the fabrication of field-effect transistors (FETs) that are indispensable for probing of carrier transport properties, accumulation of charge and interfacial phenomena. This paper reports a fabrication and characterization of TMDC FETs with heavily-doped silicon-on-insulator substrate. The silicon processing is sophisticated technology that can be extended to the reliable operation of TMDC FETs with high reproducibility. In this presented approach, the heavily-doped SOI can work as a gate electrode in FETs, while the carrier injection into TMDC layer is possible by preparing overlap structure between gate electrode and source/drain contacts. The effectiveness of our approach was demonstrated through the fabrication and characterization of FETs.P-type SOI(88 nm)/BOX(145 nm) wafer was cleaned with SPM and HF solutions. For heavily-doped n-type SOI (n+ SOI), phosphorus-doped spin-on-glass (SOG) was deposited with spin coating and baked on a hot plate at 180 oC. The substrate was annealed at 1000 oC in N2 for 30 min to perform solid phase diffusion. Then, SOG was removed by 1 % HF for 30min. For heavily-doped p-type SOI (p+ SOI), B+ ions were implanted into SOI layer. Activation was performed at 1000 oC in Ar for 30 min. SOI layer was patterned by chemical dry etching with CF4/O2. Thermal SiO2 was grown by dry oxidation at 900 oC for 10 min. Next, AlOx was deposited by RF sputtering. After contact opening with 1 % HF, Al (20 nm)/TiN (20 nm) were deposited by RF sputtering and lift-off for electrical contact to SOI. The substrates were subjected to annealing in forming gas at 420 oC for 30 min to improve the quality of gate dielectrics and electrical contact of gate pad. Al (10 nm)/Au (40nm) was deposited by thermal evaporation and lift-off for contact electrodes. Subsequently, the substrate was exposed to oxygen plasma to form hydroxyl groups on the surface of AlOx. Then, the substrate was immersed into 2-propanol containing 5 mM n-octadecylphosphonic acid (ODPA) for 6 hours at room temperature. Annealing was conducted at 100 oC in N2 for 30 min to stabilize ODPA. The gate dielectrics consists of hybrid ODPA/AlOx/SiO2. Mechanically exfoliated WS2 was transferred to the substrate with the PDMS elastomer. Finally, devices were annealed in N2 at 150 oC for 30 min to improve source/drain contact.The FET operation was observed for both n+ and p+ SOI gate. The threshold voltage (Vth) was evaluated by linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 0.05 V. In the case of n+ SOI gate electrode, the Vth of -0.71 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 150 mV/dec were evaluated. On the other hand, the Vth of -0.13 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 107 mV/dec were obtained for p+ SOI gate electrode. The difference in Vth between n+ and p+ SOI gate electrodes is derived from the difference in the Fermi level of SOI. The proposed method is suited for research in electrical characteristics of various TMDC semiconductors.

A Novel Localized-Trapped-Charge-Induced Threshold Voltage Model for Double-Fin Multi-Channel FETs (DFMcFETs)

With the effects of localized trapped charges on the flat-band voltage, a novel localized-trapped-charge-induced threshold voltage model for the double-fin multi-channel FET (DFMcFET) is presented based on the quasi-3-D scaling equation and minimum bottom-central potential. It is shown that the deep trench of the DFMcFET is superior to the shallow one in respect of reducing the localized-trapped-charge-induced threshold voltage degradation (LTTVD). Besides, the low drain voltage ${V_{\mathrm{ ds}}}$ , the low trapped charge density ${N_{f}}$ , the small damaged zone near the drain side ${L_{s}}$ and the thin gate oxide ${t_{\mathrm{ ox}}}$ are required to resist LTTVD as the normalized damaged zone is increased. The LTTVD can be well controlled by the scaling theory. With the fixed damaged zone and trapped charge density, the allowable minimum channel length can be uniquely determined according to the criterion of scaling factor. In comparison to the conventional FinFET, DFMcFET not only provides more conducting channel, but also suffers less threshold voltage degradation caused by the short-channel effects irrespective of trapped charge polarity. With its computational efficiency and simple form, the model can be easily used for the circuit application for DFMcFET.

P‐12: Extraction of Sub‐Gap Density of States for Deteriorated Oxide Semiconductor TFTs

We propose an extraction method of sub‐gap density of states (sub‐gap DOSs) for deteriorated oxide semiconductor thin‐film transistors (TFTs). Since the sub‐gap DOSs in the TFTs are high, the potential in the channel oxide semiconductor must bend under depletion and accumulation operations even if the drain current is low. In this method, the band‐bending is considered and the DOSs of such the TFT can be extracted from one transfer curve at low drain voltage. This method is simple and useful to evaluate the maximum values of the DOSs.