Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

Haiwu Xie,Shupeng Chen,Hongxia Liu,Shulong Wang,Tao Han

doi:10.3390/app9194104

Abstract

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Highlights

Advancement in the semiconductor industry has increased the demand for nanoscale devices for analog/ radio frequency (RF) and high switching speed applications, but, power consumption and reliability issues are the major concerns in integrated circuits (ICs), so compactness in devices is an urgent problem to be solved in nanoscale systems
Of 13 source region and has a larger workfunction than control gate (CG) for inducing a P+ source while CG3 is located at the middle for at inducing an intrinsic channel, InAs/GaAs is introduced at the
0.9 heterostructure located the middle for inducing an intrinsic channel, 0.1Sb0.9 heterostructure is source–channel and a heavyinterface dopingand is considered in the silicon body with concentration of introducedinterface at the source–channel a heavy doping is considered in the silicon body

Summary

Introduction

Advancement in the semiconductor industry has increased the demand for nanoscale devices for analog/ radio frequency (RF) and high switching speed applications, but, power consumption and reliability issues are the major concerns in integrated circuits (ICs), so compactness in devices is an urgent problem to be solved in nanoscale systems. According to Moore’s law, drastic reduction in volume and cost of the devices will occur. As the conventional metal oxide semiconductor field effect transistors (MOSFETs) scale down continuously, the OFF-state current dramatically increases and short channel effects (SCE) are severely aggravated, and a limitation of 60 mV/Dec subthreshold swing (SS) cannot be broken. Low switch ratio (Ion/Ioff) ratio and drain induced barrier lowering (DIBL) effect are arising. In order to avoid these issues, a lot of novel structures have.

Methods

Results

Conclusion