Abstract

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.

Highlights

  • Most of the studies about hot-carrier effects concentrated on n-MOSFETs rather than p-MOSFETs because the hot-carrier induced problems are more serious in nMOSFETs due to longer mean free path, higher energy of electrons

  • Some of the hot carriers generated in the bird's beak area are injected into the gate oxide and the others constitute the substrate current

  • The majority of hot carriers injected into the gate oxide is collected by the gate electrode and constitute the gate current

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Summary

Introduction

Most of the studies about hot-carrier effects concentrated on n-MOSFETs rather than p-MOSFETs because the hot-carrier induced problems are more serious in nMOSFETs due to longer mean free path, higher energy of electrons. The lifetime of a SC p-MOSFET is found to correlate with I, over a wide range of V Using this correlation and a gate current model based on the lucky electron approach, the lifetime of a SC p-MOSFET under pulse stress can be estimated [4]. The substitution of the bipolar device with the PLDMOS transistor leads to several advantages such as a lower minimum operating voltage, higher efficiency operation and lower heat dissipation. In this case, the use of the n-channel lateral DMOS transistor would need some more circuitry and cannot be used in open loop conditions [2]

Experimental setup
Gate current model
Results and discussion
Conclusion

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