Physical understanding and modelling of new hot-carrier degradation effect on PLDMOS transistor

Abstract

Hot carrier injection, inducing source-drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and high drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ), reduction of the on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) is observed [1, 5]. However, it has never been observed before, that the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.