P-Channel and N-Channel Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Ultralow Power CMOS

Abstract

In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.