Lateral DMOS Research Articles

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

A novel Si/SiC heterojunction Lateral Double-diffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,SP</sub> of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of Cov. LDMOS to 24.0mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , decreased by 27.7%. Furthermore, the figure-of-merit (FOM = BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm2, which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit* *Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

Hot-Carrier-Induced Degradation and Optimization for 700-V High-Voltage Lateral DMOS by the AC Stress

Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is found that there are different degradation mechanisms with different amplitudes of ac gate stress, including the maximum operating gate voltage ( ${V}_{{\text {gmax}}}$ ) stress and the maximum substrate current ( ${I}_{{\text {submax}}}$ ) stress. For the ${V}_{{\text {gmax}}}$ condition, the ON-resistance ( ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) decreases first and increases finally, which is attributed to two competitive degradation mechanisms. One is the hot holes injection at the bird’s beak during the gate pulse edges, and the other one is the hot electrons injection nearby the drain during the high state level of gate pulse. However, for the ${I}_{{\text {submax}}}$ stress, the dramatical injection of hot electrons nearby the source-metal edge during the high state level of gate pulse is always the main degradation mechanism, resulting in a monotonous increase of $\text {R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . Moreover, the threshold voltage ( ${V}_{{\text {th}}}$ ) degradations could be neglected due to the intact channel region under the ${V}_{{\text {gmax}}}$ and ${I}_{{\text {submax}}}$ conditions. In this way, the ${I}_{{\text {submax}}}$ condition is regarded as the worst stress, and an improved device with a linear-doped buried-p-well (BP) structure beneath the P-body has been proposed to restrain the degradation under the worst stress condition.

A breakdown model of LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology

An analytical model for the breakdown voltage (BV) of a Lateral Double-diffused Metal Oxide Semiconductor field-effect transistor with a Multi-Ring structure (M-R LDMOS) is presented. The proposed analytical model is obtained by solving Poisson’s equation in cylindrical coordinates, which can reasonably explain the modulation effect of the M-R structure on the surface and vertical electric field distributions at the same time, and accurately describe the potential and electric field distributions of the M-R structure. As well as the lateral, vertical and radial BVs are formulized to predict the breakdown behaviors. In the paper, all the analytical results can be validated by numerical results obtained by Sentaurus Technology Computer Aided Design (TCAD) simulation, showing the accuracy of the proposed model. It is worth noting that the proposed analytical model is applicable to lateral power devices with an M-R structure.

Effect of Charge Partitioning on IM3 Prediction in SOI-LDMOS Transistors

In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results.

Taste sensor based on the floating gate structure of a lateral double-diffused metal-oxide semiconductor

This study reports the evaluation of taste sensor applications using a lateral double-diffused metal-oxide semiconductor (LDMOS) with floating gate structures. This is the first study to use a LDMOS device, coated with a lipid membrane, to detect multiple tastes. The proposed device is manufactured based on a standard complementary metal-oxide semiconductor (CMOS) logic process and has a floating-gate structure for targeting sensor applications. Lipid membranes of Methyltrioctylammonium chloride (TOMA), Oleylamine (OAm), Decyl alcohol (DA), Oleic acid (OA), and Dioctyl phosphate (DOP), with different reactivities, were used to observe the drain current changes at various concentrations (1 fM–1 mM) of the five taste substances: sourness, bitterness, sweetness, saltiness, and umami. The experimental results show that the sensor can operate over a wide and dynamic range (1 fM–1 mM), exhibits a very low-detection limit of 1 fM, and can classify five substances with different tastes. Thus, this study demonstrates that the proposed device is suitable for application as a taste sensor.

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) and substrate doping concentration (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), the turn-off nonbreakdown time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nonbv</sub> ) of the device with higher P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> decreases faster. However, the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nonbv</sub> with higher P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> is higher at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . Therefore, the maximum T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nonbv</sub> can be obtained by optimizing N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> under a given V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . In addition, T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nonbv</sub> is greatly reduced with increasing temperature.

Novel SiC/Si heterojunction LDMOS with electric field modulation effect by reversed L-shaped field plate

A novel SiC/Si heterojunction lateral double-diffused metal-oxidesemiconductor (LDMOS) with a reversed L-shaped field plate and a stepped oxide layer has been proposed to improve the tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). The reversed L-shaped field plate is applied to modulate electric field distribution to make the breakdown occur in the low electric field area (SiC/Si interface), which increases the BV and decreases the Ron,sp of the device. Furthermore, a stepped oxide layer is used to cover the Si drift region and reshape the lateral electric field distribution by introducing a new electric field peak, which consequently enhances the BV. The simulated results have indicated that the BV of this proposed SiC/Si LDMOS increased from 226 V and 720 V to 992 V compared with the conventional Si LDMOS and SiC LDMOS, respectively, while maintaining a low Ron,sp of 27.62 mΩ·cm2.

A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer

In order to better shield the substrate-assisted depletion (SAD) effect and improve the breakdown voltage of super-junction (SJ) devices, an SJ lateral double-diffusion metal oxide semiconductor device with a gradient charge compensation layer (gradient device) is proposed. The main feature of this structure is to introduce a gradient charge compensation layer between the SJ layer of a conventional device and the substrate. The depth of the gradient charge compensation layer increases gradually from the source to the drain. The charge distribution in the drift region is optimized by reducing the compensation charge on the side near the source and increasing the compensation charge on the side near the drain. Introduction of the layer improves shielding of the SAD effect, and the electric field on the surface of the structure is an approximately rectangular distribution, thus the breakdown voltage is improved. The simulation results show that the gradient device has 409-V breakdown voltage and a 9.5-MW cm−2 figure of merit with a drift region length of 21 μm. Compared with the conventional SJ structure (conventional device) with the same drift length, the breakdown voltage and figure of merit of the gradient device are increased by 57.3% and 137.5%, respectively.

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance ( R on,sp ). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figure-of-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

Hot-Carrier-Induced Degradation and Optimization for Lateral DMOS With Split-STI-Structure in the Drift Region

The lateral double-diffusion MOS with split shallow trench isolation structure (split-STI LDMOS) in the drift region has been investigated under two hotcarrier stresses including the maximum bulk current stress (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> ) and maximum operating gate stress (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> ). For the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition, the main damage point causing the degradation of RON is found at the STI corner closest to the source with the interface state generation. In addition, the hot hole injection is found at the edge of the shrinking poly-gate region. For the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> stress condition, the main damage point causing the degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> is found at the two STI corners with interface state generation. Due to the more serious degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition is regarded as the worst-case stress condition. The novel structure with the H-shape STI in the drift region is proposed. It is demonstrated that the H-shape STI structure is effectively helpful to alleviate the hot-carrier degradation without altering the tradeoff between the OFF-state breakdown voltage and specific ON-resistance.

Design and optimization of 30 V fully isolated nLDMOS with low specific on-resistance for HVIC applications

In this paper, a novel 30 V fully isolated n-channel lateral DMOS (nLDMOS) with low specific on-resistance (RON,sp) is proposed and experimentally realized using 0.35 µm Bipolar-CMOS-DMOS (BCD) process. We optimized the process parameters, such as doping concentration of the high-voltage drift n-well (HVNW) layer, P-buried layer (PBL) and pre deep n-well (Pre-DNW) layer, for achieving a superior tradeoff between high breakdown voltage (BV) and the low RON,sp. The proposed nLDMOS is fully isolated from the substrate to support negative bias to drain and has a very lower RON,sp than other competitors in the similar technology, which is critical for devices used in high-voltage, high-current switching applications such as HVIC's. The fabricated device exhibits a BV of 42 V with RON,sp as low as 15 mohm-mm2 . Besides, the new structure is fully compatible with standard 0.35 µm BCD technology, with a margin of up to 15% in process variation, which is large enough to meet the industrial requirement for mass production. Hence, it is not only high performance but also a low-cost solution.

PSJ LDMOS with a VK dielectric layer

A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable- k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low- k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance ( R on,sp ). Furthermore, according to an enhanced dielectric layer field, low- k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.

High-Voltage Lateral Double-Diffused Metal-Oxide Semiconductor with Double Superjunction

A high-voltage lateral double-diffused metal-oxide semiconductor with double superjunction (DSJ LDMOS) is proposed in this paper. A vertical SJ under the drain and a lateral SJ in the drift region are introduced to form a double SJ in the DSJ LDMOS. To suppress the substrate-assisted depletion effect of the lateral SJ, a charge compensation layer linearly doped from source to drain is adopted in the drift region. In off-state, the vertical SJ enhances the depletion of the substrate to improve the vertical breakdown voltage (BV) and modulates the lateral electric field to increase the lateral BV. The lateral SJ increases the lateral BV and modulates the vertical electric field to improve the vertical BV. The vertical SJ is composed of N and P pillars with different concentrations. In on-state, the lateral SJ also provides a low-resistance channel, which decreases the specific on-resistance (Ron,sp). Simulation results indicate that the BV, figure of merit (FOM), and Ron,sp of the DSJ LDMOS are 1138 V, 10.5 MW cm−2, and 103.4 mΩ cm2, respectively. The BV and FOM of the DSJ LDMOS are increased by 31.3% and 483% compared with the conventional vertical SJ LDMOS (Con. VSJ LDMOS), while the Ron,sp of the DSJ LDMOS is reduced by 70%. The “silicon limit” is thus broken by the DSJ LDMOS.

A 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m LDMOS With Excellent Ronsp and Uniformity by Optimized Manufacture Process

In this paper, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~{\mu }\text{m}$ </tex-math></inline-formula> n-type lateral DMOS (LDMOS) is researched. By optimized manufacture process and device structures, ultra-low specific on resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm {onsp}}$ </tex-math></inline-formula> ) is achieved. Pbody and n-type drift region are all full self-aligned implantation (FSAI). For different structures, the uniformities of the dc parameters affected by the process variation are researched. Experimental results show that: by optimizing manufacture process and device structures, the FSAI nLDMOS has competitive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm {onsp}}$ </tex-math></inline-formula> compared with other technologies. For Breakdown voltage equals to 42 V and 52 V, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\mathrm {onsp}}$ </tex-math></inline-formula> are 18.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}{\Omega \bullet }$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m} {\Omega \bullet }$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. For FSAI-nLDMOS, both simulation and experiment demonstrated that the shift of the dc parameters generated by the process variation is superior to the other technologies. Moreover, only one n-type drift region with filed oxide is used. The device is fabricated in bulk-silicon without epitaxy. These leads to the low cost of the fabrication.

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate**Project supported by the National Natural Science Foundation of China (Grant No. 61464003) and the Guangxi Natural Science Foundation, China (Grant Nos. 2015GXNSFAA139300 and 2018JJA170010).

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 mΩ·cm2 to 23.24 mΩ·cm2 and the Baliga’s figure of merit (FOM) of is 9.07 MW/cm2.

Numerical Analysis of the LDMOS With Side Triangular Field Plate

A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage ( BV ) and reducing the specific on-resistance ( $R_{on,sp}$ ). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV . Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the $R_{on,sp}$ . The simulation results indicate that the BV of 379 V and the $R_{on,sp}$ of 37.3 $\text{m}\Omega \cdot $ cm2 are achieved by the STFP-LDMOS. The figure of merits ( FOM ) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the $R_{on,sp}$ and BV .