Abstract

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Highlights

  • LDMOS transistors have become dominant in power management IC applications due to good electrical performance and ease of integration

  • All LDMOS transistors contain an undesired, parasitic bipolar junction transistor (BJT) [1] that has a negative effect on the host LDMOS

  • When the base-emitter junction is forward biased to 1V, the Hybrid Source LDMOS collector current is 4 decades lower than the conventional PN source LDMOS

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Summary

INTRODUCTION

LDMOS transistors have become dominant in power management IC applications due to good electrical performance and ease of integration. Efforts have been made over the decades to suppress the impact of the parasitic bipolar, which usually involved the use of a highly doped body to reduce the BJT base resistance and delay the triggering of the BJT [1,2,3]. Novel approach is to utilize a Hybrid Source LDMOS architecture to provide unparalleled bipolar suppression. An improved overall architecture is presented to further enhance the performance, culminating in more than tenfold improvement of the BJT trigger current at grounded gate conditions. This improved Hybrid Source LDMOS device architecture has been implemented on an existing 0.18μm BCD on SOI Automotive Process [5]. In addition to demonstrating performance improvement, supplementary insight into the creation of the Hybrid Source and its underlying mechanisms is provided

Background and Device
Hybrid Source LDMOS Process Flow
Parasitic BJT
TRANSMISSION LINE PULSE PERFORMANCE
TCAD SIMULATION
Findings
CONCLUSION

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