Junction-gate Field-effect Transistor Research Articles

A 69-mΩ 600-V-Class Hybrid JFET

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

2D array of cold-electron nanobolometers with double polarised cross-dipole antennas.

A novel concept of the two-dimensional (2D) array of cold-electron nanobolometers (CEB) with double polarised cross-dipole antennas is proposed for ultrasensitive multimode measurements. This concept provides a unique opportunity to simultaneously measure both components of an RF signal and to avoid complicated combinations of two schemes for each polarisation. The optimal concept of the CEB includes a superconductor-insulator-normal tunnel junction and an SN Andreev contact, which provides better performance. This concept allows for better matching with the junction gate field-effect transistor (JFET) readout, suppresses charging noise related to the Coulomb blockade due to the small area of tunnel junctions and decreases the volume of a normal absorber for further improvement of the noise performance. The reliability of a 2D array is considerably increased due to the parallel and series connections of many CEBs.Estimations of the CEB noise with JFET readout give an opportunity to realise a noise equivalent power (NEP) that is less than photon noise, specifically, NEP = 4 10−19 W/Hz1/2 at 7 THz for an optical power load of 0.02 fW.

Note: A high dynamic range, linear response transimpedance amplifier

We have built a high dynamic range (nine decade) transimpedance amplifier with a linear response. The amplifier uses junction-gate field effect transistors (JFETs) to switch between three different resistors in the feedback of a low input bias current operational amplifier. This allows for the creation of multiple outputs, each with a linear response and a different transimpedance gain. The overall bandwidth of the transimpedance amplifier is set by the bandwidth of the most sensitive range. For our application, we demonstrate a three-stage amplifier with transimpedance gains of approximately 10(9)Ω, 3 × 10(7)Ω, and 10(4)Ω with a bandwidth of 100 Hz.

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I– V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.

Hybrid optically and electrically controllable field effect transistor based on manipulated nanoparticles

The hybrid optically and electrically controllable field effect transistor is a novel device whose current-voltage ( I-V ) curve can be controlled by optical or electrical modulation of metallic nanoparticles. The basic structure of this transistor is similar to that of a junction gate field effect transistor, where the conventional gate contact is replaced by an array of nanoparticles located on the upper side of the p-n junction and parallel to the channel direction, whereas the source and the drain contacts remain the same. The deposition of the nanoparticles is achieved by self-assembly using the focused-ion-beam technology. The displacement of the nanoparticles along the air gap is performed either optically or electrically. Optical control is based on a special type of optical tweezers realized by guiding and confining light into a nanosize void structure in which the nanoparticle is placed. Electrical control via an external electric field tunes the nanoparticles. Control of the I-V curve controls the logic function of the device.

DIFFUSION PROCESS IN A TRANSISTOR USING THE BOUNDARY ELEMENT METHOD

The diffusion process in a transistor is simulated by two partial differential equations: Laplace's and Poisson's. The proposed solution consists in an iterative scheme for a determination of the interface between these two equations.The first one consists in the use of an adjoint potential for the reduction of the domain to the boundary integral. The second method consists in a an analytical reduction of the domain integral and a numerical evaluation of the boundary integral using Simpson's rule and Gauss quadrature scheme. The two methods are applied to a free boundary value problem : A Junction Gate Field Effect Transistor. The results obtained are analysed and compared.

Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization

We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

High-voltage junction-gate field-effect transistor with recessed gates

A new recessed-gate structure for vertical-channel junction field-effect transistors (JFET's) is described together with a self-aligned gate-source process developed to fabricate these devices. Using this technology, devices with groove depths ranging from 8 to 18 µm have been fabricated. The characteristics of these devices is described as a function of the groove depth. It has been found that the devices display pentode-like characteristics at low gate voltages and triode-like characteristics at high gate voltages. The blocking gain has been found to increase with groove depth. However, this is accompanied by an increase in the on-resistance and a decrease in the saturated drain current. Devices with gate breakdown voltages of up to 600 V have been fabricated with the recessed-gate structure. These high-voltage field-effect transistors (FET's) have a unity power gain cutoff frequency of 600 MHz and gate turn-off times of less than 25 ns.

A new approach to model d.c. and a.c. characteristics of junction gate field effect transistors

A field dependent mobility model for use in quasi-unidimensional numerical analysis of JG FET is proposed. This model takes into account the electrical data (mobility and diffusion laws vs electric field) obtained on Si bulk material, the technological data given by the manufacturer (geometry of the mask) and the assumption of an isotropic diffusion of the gates. The static and the dynamic behaviour of the JG FET is obtained. The validity of the present model is demonstrated using very different geometrical JG FET structures. Reasonable agreement is found between calculated and experimental results up to the saturation range.

A power junction gate field-effect transistor structure with high blocking gain

A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability.

Noise of hot carriers in the channel of n silicon junction gate field effect transistors

At 77 K the noise current spectral density of n type silicon channel junction gate field effect transistors is about 70 times higher than predicted by the theory. This discrepancy is explained by the authors taking into account the noise temperature of hot electrons which is measured for n Si at 77 K vs the electric field. The theory of noise in FETs is subsequently modified and gives results in reasonable agreement with the experiment. This theory can be applied to every one dimensional device.

Noise of hot carriers in the channel of [formula omitted] silicon junction gate field effect transistors : J. P. Nougier, D. Sodini, M. Rolland, D. Gasquet and G. Lecoy. Solid-St. Electron.21, 133 (1978)

Noise of hot carriers in the channel of [formula omitted] silicon junction gate field effect transistors : J. P. Nougier, D. Sodini, M. Rolland, D. Gasquet and G. Lecoy. Solid-St. Electron.21, 133 (1978)

G-R noise and microscopic defects in irradiated junction field effect transistors

Measurements and analysis of noise in electron bombarded Junction Gate Field Effect Transistors (JFETs) in the temperature range of 300-90°K are presented. The noise frequency spectra in the range of 100–600 kHz have been predicted theoretically, using the reported values of defect energy levels and capture cross sections. Excellent matching has been observed between the theoretical and measured noise spectra. A numerical analysis reveals that, except at room temperature, the generation recombination (g-r) noise due to the Shockley-Reed-Hall (S-R-H) centers in the depletion region is negligible as compared to that in the channel. It is also shown that noise measurements and analysis can be used as a tool in the determination of microscopic parameters such as the defect energy levels, capture cross sections and the density of defects, in radiation effect studies on semiconductors.

Quantum mechanical calculation of the carrier distribution in the channel of a junction gate field effect transistor

physica status solidi (a)Volume 31, Issue 1 p. K37-K40 Short Note Quantum mechanical calculation of the carrier distribution in the channel of a junction gate field effect transistor N. Saleh, N. Saleh Department of Electrical Engineering, Faculty of Engineering, Ain Shams University, Abbassia, CairoSearch for more papers by this authorT. Ezzat, T. Ezzat Department of Electrical Engineering, Faculty of Engineering, Ain Shams University, Abbassia, CairoSearch for more papers by this author N. Saleh, N. Saleh Department of Electrical Engineering, Faculty of Engineering, Ain Shams University, Abbassia, CairoSearch for more papers by this authorT. Ezzat, T. Ezzat Department of Electrical Engineering, Faculty of Engineering, Ain Shams University, Abbassia, CairoSearch for more papers by this author First published: 16 September 1975 https://doi.org/10.1002/pssa.2210310150AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Volume31, Issue116 September 1975Pages K37-K40 RelatedInformation

Generation-recombination noise of junction-gate field-effect transistors

The generation-recombination noise of junction-gate field-effect transistors is calculated taking into account the variable mobility. The field dependence of mobility suggested by Trofimenkoff is used, and the resultant spectral intensity of the drain-noise fluctuations shows no signs of a logarithmic singularity at saturation. The need for any cutoff procedure to remove the logarithmic singularity at saturation is therefore removed, and it is thus an improvement over earlier methods.

Effects of electron bombardment on the noise in junction gate field effect transistors

The effects of electron bombardment on the various noise sources in n-type channel and p-type channel junction gate field effect transistors (JFET's) have been investigated in detail. It is shown that generation recombination ( g- r) noise is the most sensitive noise source to electron bombardment. The noise frequency spectra obtained after each bombardment level are shown to be characterized by two distinct time constants, one due to traps in the gate channel depletion region and the other due to traps in the channel.

Characteristics of the junction-gate field effect transistor with short channel length : T. L. Chiu and H. N. Ghosh. Solid State Electron.14 (1971), p. 1307

Characteristics of the junction-gate field effect transistor with short channel length : T. L. Chiu and H. N. Ghosh. Solid State Electron.14 (1971), p. 1307

Gridistor development for the microwave power region

Multichannel junction-gate field-effect transistors and their advantages were introduced in 1964 under the name Gridistor. This included both vertical and horizontal channel structures. They were developed in order to combine in the same device the advantages of field-effect and bipolar transistors. The horizontal channel structure had performance which was quite useful in the power VHF band, but it was clear that for the higher frequency and power region the vertical channel structure would be basically more suitable. However, to develop this structure for the microwave power region an exhaustive investigation had to be undertaken with a view toward eliminating its drawbacks, namely the relatively high grid resistance and also differential drain conductance. The first problem was solved by modifying the grid geometry and increasing the grid bulk impurity concentration, and the second by providing an appropriate gradation of the source and drain layer resistivities. Thus, with the usual technology and moderate grid fineness, but with optimized grid geometry, an operating frequency above 1 GHz was attained, f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> being ∼5 GHz, with a frequency-power product of ∼5 GHz. W for a single-chip Gridistor. The features of the devices produced are discussed and a complete set of experimental results is provided. Finally, new developments now being initiated with the expectation of attaining in the near future an operating frequency of 8 GHz in the power region of 1 to 2 W are outlined. An anticipated structure, which will approach the ultimate limits of the Gridistor, is also discussed. This paper deals only with the experimental part of the problems concerning the Gridistor.

Characteristics of the junction-gate field effect transistor with short channel length

A two-section model of a junction-gate field effect transistor with short channel length was derived. In this model, the current conducting channel is divided into a source and a drain section. The gradual channel approximation with a modification to include the hot electron effect is assumed applicable in the source section. The velocity saturation transport with excess carrier accumulation effect is formulated for the drain section. The normalized design curves and the characteristics of two sample devices are presented.

Correction to "Excess gate current in a junction-gate field-effect transistor"

Correction to "Excess gate current in a junction-gate field-effect transistor"