Junction-gate Field-effect Transistor Research Articles

Anomalous noise behavior of the junction-gate field-effect transistor at low temperatures

Measurements are reported on the noise resistance and the noise conductance of the junction-gate FET in the temperature range 77°K-400°K. At low temperatures anomalous noise behavior has been observed. The measurements are discussed in the light of existing theories and, when necessary, the theoretical model has been extended. The agreement is satisfactory. Generally the extra noise is caused by mobility saturation, increased free-carrier temperature, free-carrier trapping and multiplication effects in the pinched-off region. Finally, several applications are discussed in relation to the limiting noise sources.

High-frequency equivalent circuits of junction-gate field-effect transistors

Series integration of the j.f.e.t. equation makes it possible to obtain a sequence of equivalent circuits of growing complexity and accuracy but of similar structure, valid beyond pinchoff. In particular, a 5-component circuit is proposed which is useful well above the 1/τ0 angular frequency (τ0 being the transit time in the channel) and, moreover, is readily deduced from the traditional 3-component equivalent circuit.

Current-voltage characteristics of the junction-gate field-effect transistor with field-dependent mobility

Current-voltage characteristics of the junction-gate field-effect transistor are analyzed based on a depletion layer model of the channel which is divided into subregions of constant mobility and of field-dependent mobility to reproduce the actual situation under various voltage conditions in order to clarify the effect of field-dependent mobility on the characteristics of the device. New formulas for design parameters are given and experimentally verified on specially designed and fabricated samples as well as on commercial samples. Agreement between theory and measurement is good.

Junction-gate FET RF power amplifier

A junction-gate power field-effect transistor of recent design has been found to yield greater than 25 watts CW at 30 MHz in two modes of circuit configuration. In this investigation, favorable characteristics are explored for potential device utility as a high-reliability low-distortion RF power amplifier.

Excess gate current in a junction-gate field-effect transistor

Approximate potential distribution near the drain of the junction-gate field-effect transistor (JFET) is found and is used to deduce the excess reverse gate current, based on the assumption that such current is caused by an avalanche multiplication of carriers in the channel. Theory agrees well with measurement.

Lumped model analysis of the low frequency generation noise in gold-doped silicon junction-gate field-effect transistors

The theory of the generation-recombination noise due to trapped charge fluctuation at impurity centers in the transition regions of the junction gate field effect transistors is presented using the lumped equivalent circuit model introduced by Sah. The divergence of the noise power in the saturation range is avoided automatically by the lumped model which gives about 20 percent higher noise resistance value than that obtained from the previous model using analytical cut-off procedure in the gradual channel approximations. Very good agreement between theory and experiments on gold-doped silicon devices are obtained. An excess generation noise component observed near complete channel cut-off is not accounted for by the theory. In addition, a generation noise component (with corner frequency about 5 kHz) due to the presence of high concentration of mobile carriers in the edge of the transition regions is observed. Optimum low noise situation is also discussed.

General theory for pinched operation of the junction-gate FET

A device oriented model is developed to describe the operation of the junction-gate field-effect transistor (FET) beyond pinch-off. The model is derived on the basis of a generalized structure with an arbitrary channel doping profile. It provides a qualitative and quantitative description of the current conduction mechanism, and is applicable over the entire dynamic range of device operation. Current conduction mechanisms in the vicinity of the source and the drain are examined separately. It is shown that the saturation of carrier drift velocities at high electric fields results in formation of a drain space-charge region of finite length. An approximate solution of the two-dimensional Poisson's equation is developed to describe the potential distribution within this region. A significant result of the device model is the prediction of a finite drain resistance in pinched operation, which shows a strong dependence on the device operation point.

Pinched-mode operation of field-effect transistors

A device-oriented model is developed to describe the operation of the junction-gate field-effect transistor (FET) beyond pinch-off.

Current saturation and drain conductance of junction-gate field-effect transistors

The current saturation phenomena in the junction-gate field-effect transistor is analyzed using a two-section model for the conduction channel (a neutral and a depleted section) and the depletion model in the gate-junction transition region. The electric field along the channel, the electrostatic potential and the drain conductance are matched at the boundary of the two sections. Discontinuities of the drain current and conductance vs. the drain voltage characteristics near the drain current saturation points, which occurred in the simple matching procedure employed by Shockley, are removed. The computed drain resistance shows approximately a linear dependence on the drain voltage in the saturation region which is also demonstrated by the asymptotic solutions of large L/D (channel length/physical channel width), and it is proportional to L/D. Two impurity concentration profiles are studied which are the step-step (or abrupt) and the step-linear profiles for the double gate device structures. Experimental measurements of the saturation drain R-V characteristics for many silicon devices of both large (about 10) and small (about 1.5) L/D ratios are in good agreement with the theoretical analysis.

Field-dependent mobility effects in the excess noise of junction-gate field-effect transistors

According to Sah's theory (1964) of excess noise in junction-gate field effect transistors the equivalent saturated diode current Ieq of the drain noise should vary as Vd <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5/2</sup> below saturation (where Vd is the drain to source voltage) and rapidly turn over into its saturated value at saturation. Experimentally, one finds in many units that Ieqa ries as Vd <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5/2</sup> at low currents, roughly as Vd <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3/2</sup> at intermediate currents and that IeQ gradually turns over into its saturated value at saturation. We shall see that this behavior can be explained by field-dependent mobility effects.

Switching characteristics of m.o.s. and junction-gate field-effect transistors

The nonlinear differential equations describing the large-signal switching behaviour of field-effect transistors (f.e.t.s) are derived. They are shown to be analogous to those of an RC transmission line having uniform linear resistance but nonlinear capacitance per unit length. Solutions of these equations, based on an effective linear-capacitance approximation, are obtained and applied to the cases of metal-oxide-semiconductor transistors (m.o.s.t.s) and junction-gate field-effect transistors. It is experimentally established that there is little difference between the response characteristics of an exact nonlinear RC distributed line, and these of a corresponding effective linear RC distributed line. Under switching conditions, the rise time associated with the short-circuit current response is shown to be smaller than the rise time associated with the open-circuit voltage response. The latter is found to be approximately equal to the small-signal channel transit time in both the m.o.s.t. and junction-gate f.e.t.

Dc characteristics of junction gate field-effect transistors

Dc characteristics of junction gate field-effect transistors

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.

Comparison of three simple field-effect-transistor models

The electrical characteristics of junction-gate field-effect transistors with a uniform, linear and parabolic distribution of impurities in the channel region are compared. The uniform distribution corresponds to an alloyed p-n junction gate, while the other two are approximations to a diffused-junction gate.

Thermal noise in junction-gate field-effect transistors

Measurements are reported on the device parameters and the noise properties of junction-gate field-effect transistors and the results are compared with theory. It is found that the high-frequency input conductance g 11 and the high-frequency gate-drain conductance g 12 vary as the square of the frequency and show practically full thermal noise. The high-frequency transconductance decreases with increasing frequency, as expected theoretically. The high-frequency output noise of the FET for short-circuited input is the sum of the low-frequency noise of the FET and the thermal noise of |g 12 |. A small correlation effect between the short-circuit gate noise and the short-circuit drain noise exists and agrees with theory. An approximate expression for the noise figure is given that is reasonably correct up to the cutoff frequency of the FET.

Charge-control analysis of m.o.s. and junction-gate field-effect transistors

Useful expressions for the small-signal forward- and reverse-transfer parameters of metal-oxide-semiconductor and junction-gate field-effect transistors are derived from a simple unified charge-control analysis which is also applicable to the bipolar transistor. Basic parameters of field-effect and bipolar transistors are compared. It is shown that, although the physical mechanisms involved in the operation of these three types of transistor are distinctly different, their electrical equivalent-circuit representation and the significance of the associated parameters are identical.

The field-effect transistor-its characteristics and applications

The characteristics of the junction gate field-effect transistor and the basic relations among its parameters are described. Some figures of merit are derived in terms of its physical parameters and the limitations considered. Applications in nuclear instrumentation are discussed. Some advantages of field-effect transistors are in high input impedance, low noise at very low and medium frequencies, and a wide operating temperature range (-200°C to +100°C). In addition, the field-effect transistor represents a new circuit element - voltage (charge) controlled conductance with fast response. Field-effect transistors are particularly suitable for low noise amplifiers at low and medium frequencies, for high input impedance amplifiers (as for integrators), for charge-sensitive amplifiers, and for analogue multipliers. They can also be applied as controllable feedback elements.

Theory of low-frequency generation noise in junction-gate field-effect transistors

The theory of the low-frequency generation noise from charge fluctuation of the Shockley-Read-Hall centers in the transition regon of the gate junction of a field-effect transistor is presented. The dominant importance of this mechanism in the transition region compared with other mechanisms in the channel (thermal noise and carrier concentration fluctuation) is shown using a simple one-dimensional model at low frequencies. The two-dimensional analysis of this noise mechanism is then worked out in the gradual channel approximation using both the electrostatic field and the lumped circuit model approaches. Nonideal effects such as surface noise and gate-junction transition region noise outside of the channel are discussed and are found to be negligible compared with this mechanism. It is shown explicitly that the previously published noise theory of the junction-gate field-effect transistors neglects the contribution from this noise source.