Integral Nonlinearity Research Articles

A 16-bit DPT-DAC over 120dBc SFDR with Signal-Phase regulation and Switching-Glitch neutralization

This paper introduces a fully-differential current steering, dynamically performance tunable digital-to-analog converter (DPT-DAC) for 5G and 6G telecommunication systems. In the DPT-DAC, a novel signal-phase regulation (SPR) technique and switching-glitch neutralization (SGN) technique are proposed to improve the dynamic performance of the DAC. In the standard 65 nm CMOS process, the simulation results show that by using the proposed SPR technique, the spurious free dynamic range (SFDR) can be tuned in the range of 97.3dBc to 122.4dBc under the best conditions. The optimized intermodulation distortion of the third order (IMD3) is −115.3dBc. By adding the extra SGN structure, we optimized the integral nonlinearity (INL) and differential nonlinearity (DNL) parameters of the DAC to 0.604LSB and 0.547LSB, respectively. Our design consumes 152mW at a working frequency of 1 GS/s, with an area of 0.62 mm2.

Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications.

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as -0.32 to 0.33 and -0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2-75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.

Linearisation of Digital-to-Analog Converters by Model Predictive Control

Digital-to-analog converters (DACs) are used to reconstruct digital quantised signals in the analog domain. Practical DACs exhibit several non-ideal effects; principally integral non-linearity (INL). INL is caused by element mismatch, meaning actual output levels deviate from the ideal, causing distortion. To reduce this error, a method employing moving horizon optimal control is proposed, where INL has been integrated into the model. The model is built by precisely measuring the INL of the physical device and organising the data into a lookup table. Previous attempts at using moving horizon optimal quantiser (MHOQ) have assumed ideal quantisation and are therefore unable to reduce the impact of INL. Several other methods exist that can linearise and mitigate the impact of INL but have significant drawbacks, such as a lack of guaranteed stability, complexity, and the need to use specialised and custom circuit topologies that cannot be replicated with of-the-shelf equipment. The effectiveness of the proposed method is demonstrated via simulations and experiments on an of-the-shelf DAC.

Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70 μm pixel pitch

This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32 × 32 pixel matrix at 70 μm pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30 %. A sub-100 ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3 MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4 Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation delays across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.

Explosive Growth of Image Sensors in Smart Government Technology and Economic Scale

CMOS image sensor is a rapidly developing image sensor product in the past decade. Relying on the advantages of process compatibility with standard CMOS process, CMOS image sensor integrates analog photoelectric photosensitive circuit and digital signal processing circuit to become a small and powerful system on chip. This article mainly studies the explosive growth of image sensors in smart government technology and economic scale. The main purpose of this article is to study the technical application of image sensors, reduce the administrative cost of social governance, improve the level of government governance, benefit the public, and realize the requirements of smart government affairs and rapid economic development of the city. This study tested the static performance of the analog-to-digital conversion circuit by inputting a limited number of sampling points, and its integral nonlinearity and differential nonlinearity were both less than 1LSB. The bandgap reference circuit provides a reference level for the entire system. It uses two PNP-type bipolar transistors parasitic in the CMOS process to achieve a temperature and voltage-independent bandgap reference voltage through the feedback of the operational amplifier. It is ideal for use In the case of resistance simulation, its accuracy reaches 16.6ppm. The scanning method of the pixel array uses multi-sampling technology to increase the dynamic range of the sensor by 2N times. The correlated sub-sampling technology eliminates the fixed pattern noise between pixel units. The use of pipelined analog-to-digital converters can achieve good resolution, speed and area compromise.Through the realization and simulation of transistor-level circuits, the performance of each part of the system meets the requirements of design and application.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

Design and analysis of 4-bit low-power, high-performance current steering DAC implemented using CNT-GDI logic

This work proposes a 4-bit unary weighted current steering digital to analog converter (CS-DAC) with minimal integral nonlinearity (INL) error, less power consumption, and low glitch area. The input to the differential switch is through the thermometer decoder designed using GDI (Gate Input diffusion) logic, which lowers the power consumption and glitch area (also known as glitch energy) to 7.7nW and 0.0038 pVs respectively. Additionally, this unary decoder is used in the digital block of the proposed CS-DAC to lower the overall space and power consumption. The proposed circuitry employs 32 nm technology CNTFET technology. The comparative analysis of the CNTFET based proposed unary decoder design has shown a significant improvement of various performance measuring parameters. The power consumption, latency, and PDP has got substantially reduced by ∼94 %, ∼86 %, and ∼99 % in comparison to the conventional MOSFET based circuitry. In addition, it has been observed that in the proposed CNTFET GDI logic-based CS-DAC the INL, and differential non linearity (DNL) have got decreased by ∼89 % and ∼92 % respectively in comparison to the conventional MOS-based CS-DAC.Further, the dynamic performance measuring parameter like Spurious Free Dynamic Range (SFDR) has got increased by 41.7 % in comparison to the conventional CS-DAC. With a single 0.9 V supply voltage, the proposed DAC dissipates ∼100 % less power as compared to conventional CMOS-based CS-DAC.

An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal ‘CLKSampling’ to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (fs)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the ‘CLKSampling’ signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical fs of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoMWN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum fs with all the sections of the ADC operating at 3.3 V. The FoMWN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

A co-simulation of superconducting qubit and control electronics for quantum computing.

As the number of qubits in quantum computing increases, the scalability of existing qubit circuit structures and control systems may become insufficient for large-scale expansion and high-fidelity control. To address this challenge, we propose a behavioral-level model of a superconducting qubit and its control electronics, followed by a co-simulation to evaluate their performance. In this paper, we present the modeling process, simulation procedure, and resulting design specifications for the qubit control system. Our co-simulation approach utilizes MATLAB and Simulink, enabling us to derive critical circuit design specifications, such as the required Digital-to-Analog Converter (DAC) resolution, which should be 8 bits or higher, to achieve high-fidelity control. By taking into account factors such as DAC sampling rates, integral and differential nonlinearities, and filter characteristics, we optimize the control system for efficient and accurate qubit manipulation. Our model and simulation approach offer a promising solution to the scalability challenges in quantum computing, providing valuable insights for the design of large-scale superconducting quantum computing systems.

Wavelet decomposition and reconstruction-based INL method for testing high-precision ADC

In traditional analog-to-digital converter (ADC) linearity testing, the cost of testing escalates in tandem with the increase in ADC resolution. This research proposes a time-efficient method for testing the integral nonlinearity (INL). Drawing on the wavelet decomposition and reconstruction technique in conjunction with sine wave histogram, our approach facilitates swift and accurate testing of high-precision ADC linearity compared to conventional methods. Our approach acquiring the initial INL result by sampling the sinusoidal histogram using a modest number of samples. Subsequently, we employ wavelet decomposition to break down the initial result into high-frequency and low-frequency portions. Setting thresholds for these components and reconstruct them to derive an accurate INL result. Experimental findings demonstrate that our proposed method effectively enhances the accuracy of high-precision ADC linearity testing. Furthermore, it reduces the linearity testing time by over tenfold and diminishes estimation errors by more than 30%. Consequently, our method establishes a more dependable means of testing for ADC design and manufacturing.

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.

In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block

A possible approach to overcome the von Neumann bottleneck and meet the increasing demand for better computing performance is to computing in-memory (CIM). The results of the in-memory calculations are primarily reflected in the vertical bitline (BL) analog voltage. However, the nonlinearity of the BL discharge deteriorates with the increase in discharge voltage. In this study, we propose a diagonal symmetry weight block (DSWB) based on an eight-transistor (8T) static random access memory (SRAM) that can achieve multibit transposable operations. In addition, to guarantee linearity and complete multibit multiplication operations, we propose a cascode current mirror (CCM)-based multiplier. To achieve low-overhead and more efficient quantification, our proposed CIM macro uses a counter-type quantization circuit to read out the analog calculation results. We simulated the performance of the proposed 8T SRAM in a 28-nm complementary metal–oxide–semiconductor process. The integral nonlinearity (INL) of the proposed CCM-based CIM decreased by approximately 54.4% compared with the traditional CIM. Furthermore, the proposed in-memory multibit multiplication throughput density was 6.74 GOPS/kb; this throughput density improvement is approximately 3.3–10.5 times higher than the existing CIM works.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs

This brief is devoted to development of a switching scheme for unary digital-to-analog converters (DACs). Switching schemes are one of possible solutions to compensate the influence of the component value deviations appearing during integrated circuit production. Previously known deterministic switching schemes have some weak points, which limit the compensation with resolution growth. In order to overcome such drawbacks, this work adapts the properties revealed and employed in switching schemes, where each element is split into several parts. Based on these properties, the novel Hierarchical Chessboard Flip (HCF) switching scheme is proposed. Simulation demonstrated that HCF reduces the integral nonlinearity (INL) better than previously known solutions while being scalable to any even bit number in DAC array. Adoption to odd resolutions is also possible. Additionally, an extension of the commonly-used simulation approach is introduced. Obtaining a dependence of INL reduction on the rotation angle of error profile may reveal a weakness of some switching scheme in spite of competitive average values.

A 6-bit Analog-to-Digital Converter for Electromyography Implemented Using N-Type Metal-Oxide Thin-Film Transistors

Consisting of more than 2000 n-type metal-oxide thin-film transistors (TFTs), a 6-bit analog-to-digital converter (ADC) adopting the subranging architecture is designed, fabricated, characterized and applied to digitize an electromyogram (EMG). Consisting of amplifiers each with a feedback stage for gain-boosting, the comparators at the heart of the ADC incorporate a scheme for compensating the offset error arising from the inevitable non-uniformity of the TFT parameters. Compared to the specifications of reported ADCs based on TFTs, a higher sampling rate of 1000 S/s, a smaller differential non-linearity of 0.76 least-significant bit (LSB) and a smaller integral non-linearity of 0.88 LSB are achieved. Since the same low-temperature TFT technology for fabricating the EMG acquisition system on a flexible substrate is used to construct the ADC, the two could be readily monolithically integrated.

Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method

The time-to-digital converter (TDC) is the primary instrument for measuring time intervals. A common solution for FPGA-based TDCs is to construct a tapped delay line (TDL) for time interpolation to produce a sub-clock time resolution. The jitter and quantization, granularity and uniformity of the delay cells, and so on in TDL, determine the achievable TDC time resolution and linearity. To achieve higher linearity, a TDL and its encoding method for compact TDC on the UltraScale FPGA is proposed in this paper. A dual-sampling method with TDL is adopted, which improves precision and efficiency by directly encoding the state of the delay line, allowing further subdivision of the delay unit in combination with wave union. The bin width of the TDL obtained based on our method is measured here using the code density calibration method and draw the integral nonlinearity and differential nonlinearity. Based on the chain structure and encoding method proposed in this article, the TDL and encoding layout have been optimized to achieve a more compatible UltraScale FPGA and can also be further applied to multi-channel TDC.

A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors

This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC). The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section decision, 4-bit coarse conversion, and finally 8-bit fine conversion with 1-bit redundancy. The conversion step is substantially reduced from conventional 4096 to 276. The linearity of the ADC is guaranteed by a stable common mode voltage of the comparator varying only within 31.25 mV. Moreover, two high-accuracy ramp calibration techniques are utilized to correct the current variation in the fine ramp and the slope error between the coarse and fine ramps. A hybrid comparator is utilized in the ADC to save power while maintaining the performance. The ADC is designed and simulated in 0.18 μm CMOS process with 7.5 μm width. The differential nonlinearity and integral nonlinearity of the proposed ADC are reduced from +0.3/-1 LSB and +3.1/-2.55 LSB to +0.3/-0.3 LSB and +1/-0.45 LSB at 61.7 kS/s sample rate by the calibrations.

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method.

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.