Abstract
This paper introduces a fully-differential current steering, dynamically performance tunable digital-to-analog converter (DPT-DAC) for 5G and 6G telecommunication systems. In the DPT-DAC, a novel signal-phase regulation (SPR) technique and switching-glitch neutralization (SGN) technique are proposed to improve the dynamic performance of the DAC. In the standard 65 nm CMOS process, the simulation results show that by using the proposed SPR technique, the spurious free dynamic range (SFDR) can be tuned in the range of 97.3dBc to 122.4dBc under the best conditions. The optimized intermodulation distortion of the third order (IMD3) is −115.3dBc. By adding the extra SGN structure, we optimized the integral nonlinearity (INL) and differential nonlinearity (DNL) parameters of the DAC to 0.604LSB and 0.547LSB, respectively. Our design consumes 152mW at a working frequency of 1 GS/s, with an area of 0.62 mm2.
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