Abstract

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal ‘CLKSampling’ to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (fs)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the ‘CLKSampling’ signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical fs of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoMWN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum fs with all the sections of the ADC operating at 3.3 V. The FoMWN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration.

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