1MS/s low power successive approximations register ADC for 67-fJ/conversion-step

Abstract

An 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented and implemented with TSMC 0.18-um CMOS process. The SAR ADC makes use of an asynchronous control circuit to internally generate the necessary clock signals to reduce half comparator and digital circuit power consumption. To avoid using a high-frequency clock generator, the proposed ADC uses an asynchronous control circuit to internally generate the necessary clock signals. The dynamic comparator generates the valid signal is the control signal of the sampling switches; it turns on the switches at high potential and turns off the switches at low potential. The average switching energy and total capacitance are reduced. Regarding that, the power consumption can be reduced to "half" by using asynchronous control circuit. Power dissipation is then minimized by optimizing the architecture and by careful design of analog circuitry. Measured results show that the proposed 8-bit SAR ADC consumes 10.3 μW with 1.8-V supply voltage. When sampling at 1.0 MSample/s, the prototype ADC achieves 45.3 dB/56.6 dB peak signal-to-noise-and-distortion ratio (SNDR)/SFDR and an effective number of bits (ENOB) of 7.23 bit. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are 0.66 LSB and 0.61 LSB, respectively. The core circuitry measures 0.205 (0.57 × 0.36) mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and including pads, the chip area occupies only 0.69 (1.03 × 0.67) mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .