An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology Application

Abstract

In this paper, a 1.8-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying SAR control logic that reduces half comparator and digital circuit power consumption, the proposed SAR ADC achieves low power consumption. Also, bootstrapped switch method is used to solve varying on-resistance of analog sampling switch caused from varying input signal. Measured results show that at the supply voltage of 1.8 V and sampling rate of 2 MS/s, the proposed SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 42.7 dB, an effective number of bits (ENOB) of 6.8 bits, a differential nonlinearity (DNL) of 0.98 LSB, an integral nonlinearity (INL) of 2.01 LSB and a power consumption of 128 µW. The overall chip area is only 0.67 mm 2 with a small ADC core area of 0.226 mm 2 for bioinformatics and computational Application.