A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications

Abstract

This paper presents a low power programmable 12-bit Two Step successive approximation register (SAR) — Flash analog-to-digital converter architecture for communication and bio-potential signal processing applications. The proposed ADC consists of two identical 6-bit SAR-Flash analog-to-digital converter (ADC) stages combined with a pipelined inter-stage gain amplifier to improve performance, reduce area, and power consumption. The 6-bit SAR-Flash ADC stage consists of low power and high performance 3-bit SAR ADC and 3-bit flash ADC. The proposed ADC architecture results are compared with recent conventional SAR ADCs and hybrid ADCs at different sampling frequencies. The ADC is designed in 90nm standard CMOS process occupies 0.1225 mm2 area. The performance parameters of the proposed ADC design are found to be differential nonlinearity (DNL) of ±0.28 LSB, integral non-linearity (INL) of ±0.52 LSB, signal-to-noise-and-distortion ratio (SNDR) of 67.4 dB, spurious-free dynamic range (SFDR) of 79.6 dB, and effective number of bits (ENOB) of 10.9 bits with input frequency of 15 MHz @ 200 MS/s sampling frequency at 1.0 V supply voltage. The power consumption of the ADC at lower sampling frequency at 500 KS/s is 1.47 pW and at 200 MS/s it is 1.35 mW.