A 600-msample/s, 25-mW, 6-bit folding and interpolating ADC in 0.13µm CMOS

Abstract

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.