An undersampling 14-bit cyclic ADC

Abstract

An undersampling 14-bit 357 kSps cyclic ADC is designed for radio frequency identification (RFID) transceiver system. Modified passive capacitor error-average (PCEA) technique is adopted for high accuracy. Opamp sharing and the removal of front-end SHA are utilized for low power dissipation and small chip area. The proposed chip is fabricated in a 180 nm CMOS process, and it occupies 0.65 mm × 1.6 mm. With 2.431 MHz input, the ADC achieves 70.4 dB signal-to-noise and distortion ration (SNDR), 85.6 dB spurious free dynamic range (SFDR) and 11.4 effective number of bits (ENOB). When the input frequency increases to 15.59 MHz, the measured SNDR, SFDR and ENOB are 67.3 dB, 88.1 dB and 10.9 bit, respectively. With 3 V supply, it consums 4.2 mW with FOM of 4.3 pJ/Step. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>