Abstract

This paper describes a 1.8-V, 8-bit, 125 Msample/s analog-to-digital converter (ADC) with a power-efficient architecture designed in a 0.18-mum CMOS technology. Through sharing an amplifier between two successive pipeline stages, the converter is realized with just three amplifiers and a separate sample-and-hold block. It employs a wide-bandwidth low-power wide-swing gain-boosting folded-cascode amplifiers, an improved bootstrap switch technique and appropriate scaling down skill. The simulation result shows the ADC achieves 57.7 -dB spurious free dynamic range (SFDR), 48- dB signal-to-noise ratio (SNR), 7.6 effective number of bits (ENOB) for 62- MHz input and consumes 36 - mw from 1.8-V supply, which also includes five buffer amplifiers.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.