Abstract
A high linearity, undersampling 14-bit 357 kSps cyclic analog-to-digital convert (ADC) is designed for a radio frequency identification transceiver system. The passive capacitor error-average (PCEA) technique is adopted for high accuracy. An improved PCEA sampling network, capable of eliminating the crosstalk path of two pipelined stages, is employed. Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area. An additional digital calibration block is added to compensate for the error due to defective layout design. The presented ADC is fabricated in a 180 nm CMOS process, occupying 0.65 × 1.6 mm2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range (SFDR), and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
