An 8-bit 20 MS/s Successive Approximation Register Analog-to-digital Converter with Low Input Capacitance

Abstract

A 1.8-V 8-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying low input capacitance that reduces driving difficulty of the ADC, the proposed SAR ADC achieves less sampling time. Also, asynchronous control logic is used which doesn’t require an external high frequency clock to drive ADC. Measured results show that at the supply voltage of 1.8 V and sampling rate of 20 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 55.1 dB, a signal-to-noise and distortion ratio (SNDR) of 44.5 dB, an effective number of bits (ENOB) of 7.1 bits, a differential nonlinearity (DNL) of 0.81 LSB, an integral nonlinearity (INL) of 1.24 LSB and a power consumption of 588 μW. Including pads, the chip area is only 0.74 (0.86 x 0.86) mm2 with a small ADC core area of 0.176 mm2.