A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communications

Abstract

In this paper, a 1.8-V 10-bit 40MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying Vcm-based switching method that reduces switching power of the DAC, the proposed SAR ADC uses less capacitor in the DAC array. Also, asynchronous control logic is used which an external high frequency doesn't need clock to drive ADC. Measured results show that at the supply voltage of 1.8 V and sampling rate of 40 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 70.56 dB, a signal-to-noise and distortion ratio (SNDR) of 55.84 dB, an effective number of bits (ENOB) of 8.98 bits, a differential nonlinearity (DNL) of 0.58 LSB, an integral nonlinearity (INL) of 1.01 LSB and a power consumption of 1.91 mW. The overall chip area is only 0.57 mm2 with a small ADC core area of 0.19 mm2.