A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

Abstract

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.