Abstract
This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.
Highlights
With the continuous development of the information society, new technologies such as augmented reality (AR), virtual reality (VR), driverless, and internet of things enter people’s lives, but the demand for more data transmission and higher communication speed follows as well
The high-speed clock distribution circuit is a key part that affects the overall performance. This design uses a clock distribution circuit based on complementary metal-oxide-semiconductor (CMOS) and current mode logic (CML), which ensures the speed and quality of the high-speed clock, and reduces the overall power consumption
A timing mismatch calibration is integrated into the chip, which can achieve fast timing mismatch detection of the input signal that is bandlimited to the Nyquist frequency, and correct the timing mismatch of each sub-analog-to-digital converter (ADC) through variable delay line (VDL)
Summary
With the continuous development of the information society, new technologies such as augmented reality (AR), virtual reality (VR), driverless, and internet of things enter people’s lives, but the demand for more data transmission and higher communication speed follows as well. In UWB communication systems, high-speed large-bandwidth analog-to-digital converters (ADCs) are the core devices which affect system performance, but it is uneasy to implement ultra-wideband high-resolution ADCs [5]. It is reliable to achieve high speed by a single-channel ADC This method will produce great power consumption due to the large current. In order to mitigate the significant degradation, a novel offset calibration that can achieve quick detection and accurate correction is proposed It does not affect the speed of the comparator, so it is suitable to use it in high-speed circuits. A timing mismatch calibration is integrated into the chip, which can achieve fast timing mismatch detection of the input signal that is bandlimited to the Nyquist frequency, and correct the timing mismatch of each sub-ADC through variable delay line (VDL).
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