Abstract
A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.
Highlights
The gigahertz sampling rate, high-resolution and power efficient analog-to-digital converter (ADC) has always been demanded in various applications such as software-defined radios, cableTVs and broadband satellite receivers [1,2,3]
When the resolution is increased to 12 bits, the sampling rate for single-channel Successive approximation register (SAR) ADC is usually limited to dozens-to-hundreds of megahertz due to its Electronics 2020, 9, 375; doi:10.3390/electronics9020375
A 1 GS/s 12-bit pipelined/SAR hybrid ADC is demonstrated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, where two multiplying digital-to-analog converter (MDAC) stages are cascaded in series to resolve the 5 most significant bits (MSBs) and the rest of 8 lower bits are resolved by time-interleaved SAR (TI-SAR) quantizer
Summary
The gigahertz sampling rate, high-resolution and power efficient analog-to-digital converter (ADC) has always been demanded in various applications such as software-defined radios, cable. For the SAR ADC with 12 bits resolution, the total sampling capacitance is generally larger than the capacitance considering the thermal noise due to the large number of unit capacitor and its size matching requirement [13] It calls for a power hungry input buffer. Because multiple channels share the same reference and operate simultaneously, the conversion in each channel interact through the reference, resulting in the signal-dependent error [14] To address these issues, a 1 GS/s 12-bit pipelined/SAR hybrid ADC is demonstrated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, where two multiplying digital-to-analog converter (MDAC) stages are cascaded in series to resolve the 5 most significant bits (MSBs) and the rest of 8 lower bits are resolved by time-interleaved SAR (TI-SAR) quantizer. A calibration scheme based on virtually-interleaved channels (VIC) is employed to correct the offset and gain mismatches, which avoids the calibration performance deterioration due to the statistical deviation of the TI-SAR input signal
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