Ge MOSFETs Research Articles

Improved electrical characteristics and reliability of Ge MOSFET device with nitrided high-k gate dielectric by plasma immersion ion implantation

MOSFET devices with Ge channel and nitridation treatment using plasma immersion ion implantation (PIII) are studied in this work. Experimental results show that the electrical characteristics and reliability of Ge MOSFETs can be significantly improved by PIII nitridation. For instance, the mobility of device with 3 nm Si cap after PIII nitridation is enhanced by about 20%. Although the driving drain current of sample with a thinner Si cap is higher, its reliability property is worse. Regarding the effects of energy in PIII nitridation, the electrical characteristics of the sample with 2 keV are better than that with 1.5 keV.

High Mobility Ge-Based CMOS Device Technologies

In this paper, we report on critical issues and possible solutions for realizing Ge MOSFETs on the Si platform. The main critical objectives in regard to Ge MOSFETs are (1) formation of high quality Ge channel layers on Si substrates (2) MIS gate stacks with much smaller EOT and interface defects (3) superior source/drain junction technology (4) combination of mobility booster technologies such as surface orientation and strain. We demonstrate that GeO2/Ge MOS interfaces can provide superior interface properties, leading to high hole and electron mobility. It is also shown that a gas phase doping technique is promising for forming superior n+/p junctions, which is critical for obtaining Ge nMOSFETs. Also, the importance of surface orientation engineering on the further mobility enhancement of Ge CMOS is addressed.

MBE—Enabling technology beyond Si CMOS

Achievement of low interfacial densities of states, small equivalent oxide thickness, high κ values, and thermal stability at high temperatures in the high κ dielectrics on high carrier mobility semiconductors, the leading candidates for technology beyond Si CMOS, has been made using MBE. This paper reviews our recent advances in meeting the unprecedented demands in materials and physics for the new technology. Moreover, self-aligned inversion-channel InGaAs and Ge MOSFETs using MBE-Ga2O3(Gd2O3) as the gate dielectric are compared favorably with those using the gate dielectrics made from other thin film techniques.

High-Mobility TaN/$\hbox{Al}_{2}\hbox{O}_{3}$/Ge(111) n-MOSFETs With RTO-Grown Passivation Layer

We report the fabrication of high-electron-mobility Ge(III) n-MOSFETs using a novel and simple approach to passivate a Ge surface by rapid thermal oxidation (RTO). A thin interfacial GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer is formed by RTO, which passivates the high-k/Ge interface. The GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -passivated n-MOSFETs fabricated using a gate-first self-aligned process with high-k/metal gate demonstrate a high peak effective mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ~ 713 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> · V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> · s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) with ~2x enhancement over control Si(100) devices. Moreover, at a drain bias of 1 V and at a gate overdrive of 1.2 V, Ge MOSFETs (L ~ 75 μm) show a drive current of ~1.1 mA/ mm, which is ~1.6 X higher than that of the control Si devices. In addition, a good subthreshold slope of ~130 mV/decade and an Jon/-Toff ratio ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> were achieved using the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer formed by RTO.

Electrical Properties of Yttrium-Titanium Oxide High-k Gate Dielectric on Ge

The feasibility of YTiOx as a high-k gate dielectric for germanium-metal-oxide-semiconductor (MOS) devices has been investigated. The effects of different concentration of TiOx on electrical properties of YTiOx-based MOS capacitors are reported. It has been demonstrated that higher TiOx concentration in YTiOx may help to boost up dielectric constant while it causes serious damage to the interfacial properties. It has been observed that YTiOx film can effectively prevent re-growth of GeOx-based interfacial layer likely due to formation of stable Y-Ti-germanate at the interface in consequence of strong interaction of YTiOx with underlying Ge substrate. Indeed, YTiOx with 22% TiOx exhibits fairly good electrical characteristics with high dielectric constant value of κ~21{plus minus}1. The potentiality of YTiOx has further been examined with gate oxide downscaling and the results are compared with that of regularly used high-κ dielectrics promising for Ge MOSFETs.

InGaAs and Ge MOSFETs with high κ dielectrics

InGaAs and Ge MOSFETs with high κ’s are now the leading candidates for technology beyond the 15 nm node CMOS. The UHV-Al 2O 3/Ga 2O 3(Gd 2O 3) [GGO]/InGaAs has low electrical leakage current densities, C– V characteristics with low interfacial densities of states ( D it ’s) and small frequency dispersion in both n- and p-MOSCAPs, thermal stability at temperatures higher than >850 °C, a CET of 2.1 nm (a CET of 0.6 nm in GGO), and a well tuning of threshold voltage V th with metal work function. Device performances in drain currents of >1 mA/μm, transconductances of >710 μS/μm, and peak mobility of 1600 cm 2/V s at 1 μm gate-length were demonstrated in the self-aligned, inversion-channel high In-content InGaAs n-MOSFETs using UHV–Al 2O 3/GGO gate dielectrics and ALD–Al 2O 3. Direct deposition of GGO on Ge without an interfacial passivation layer has given excellent electrical performances and thermodynamic stability. Self-aligned Ge p-MOSFETs have shown a high drain current of 800 μA/μm and peak transconductance of 420 μS/μm at 1 μm gate-length.

A carrier-mobility model for high- k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high- k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high- k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high- k gate dielectric and the charge carriers in the conduction channel.

Uniaxial Stress Engineering for High-Performance Ge NMOSFETs

Ge channel is one of the promising performance boosters for replacing Si channel in future complementary metal-oxide-semiconductor technology. The uniaxial stress technology can further enhance the performance of Ge MOSFETs. In this paper, the uniaxial stress effect on Ge NMOSFETs was experimentally and theoretically investigated. The gate dielectric in the Ge NMOSFETs was fabricated by using the novel radical oxidation technique. The high quality of the gate dielectric allowed high vertical field mobility measurements. By applying mechanical uniaxial stress on the fabricated Ge NMOSFETs, the mobility enhancement was experimentally obtained. The physical mechanism of mobility enhancement under such strain indicates that the device performance of Ge NMOSFETs in the ballistic transport regime can achieve as much as 48% drive current gain beyond the 15 nm technology node.

Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric

Metal–oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 × 10 11 cm −2 eV −1 close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH 3 nitridation and a subsequent N 2O treatment of an as-grown SiO 2 film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler–Nordheim (F–N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs. Most importantly, without using a Ge substrate, the SiON film on a Ge layer can be formed by the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs.

Effect of interfacial oxide on Ge MOSCAP and N-MOSFET characteristics

The effect of electrical quality of interfacial oxide on Ge MOSCAP and MOSFET characteristics is investigated. Different growth conditions are studied to optimize the interfacial layer. CV and D it measurements are done for accurate comparison of different gate dielectric stacks. Optimized ozone oxidation process is integrated with Co-induced dopant activation to fabricate Ge N-MOSFETs. Forty percent improvement in inversion electron mobility is demonstrated with optimized GeO 2 passivation. The highest electron mobility is reported in bulk Ge N-MOSFETs with GeO 2/Al 2O 3 gate dielectric stack.

Role of Carrier Transport in Source and Drain Electrodes of High-Mobility MOSFETs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have studied the performance potentials of III–V semiconductors and Ge n-channel MOSFETs based on a quantum-corrected Monte Carlo device simulation. We found that as a ballistic limit is approached, III–V MOSFETs lose their inherent advantage over Si and Ge MOSFETs because current enhancement due to ballistic transport becomes less effective than in Si and Ge channels. However, a high source and drain doping concentration was found to greatly improve the performance of III–V MOSFETs by reducing parasitic resistance and the mitigation of “source starvation” attributed to the low density of states. </para>

Improvement of Thermal Stability of Ni Germanide Using a Ni–Pt(1%) Alloy on Ge-on-Si Substrate for Nanoscale Ge MOSFETs

In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 °C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as PtxGey and NixPt1-xGey can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.

Device performance of p-Ge MOSFETs at liquid nitrogen temperature

The device performance of p-channel Ge MOSFETs at liquid nitrogen temperature is reported and initial results of room temperature irradiation with 2-MeV electrons on the cryogenic device performance is described. It is shown that at 77 K an increase of the drain current and g m is observed. This increase of the g m can be explained by considering the balance between reduced phonon scattering on the one hand and increased Coulomb scattering by interface states, on the other. After irradiation, a slight negative shift of the threshold voltage and a decrease of the drain current for input and output characteristics have been observed together with a decrease of the transconductance ( g m).

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Electrical Properties of Lanthanum-scandate Gate Dielectric Directly Deposited on Ge

The electrical performance of both Ge MOSCAP and MOSFET with LaScOx high-k gate dielectric directly deposited on Ge (100) without utilizing any interfacial passivation layer has been investigated. This study also reports about the control of Vfb/Vth through ScO concentration. Accordingly, a relatively larger hysteresis and higher density of interface states with ScO concentration having lower or higher than 50% along with increasing annealing temperatures were observed in general as a result of deterioration caused by the formation of GeOx at the interface in conjunction with more pronounce intermixing or Ge out-diffusion into LaScOx. Nevertheless, an ultrathin Si passivation layer is found to be advantageous to inhibit Ge incorporation into high-k bulk in the form of GeOx, thereby diminishing the resultant oxide charge trapping as well as improves the thermal stabilities of the entire LaScOx/Ge MOS structures. Besides, reasonably good electrical properties of Ge p-MOSFETs with LaScOx gate dielectric have been demonstrated.

High-k Dielectrics for Ge, III-V and Graphene MOSFETs

not Available.

Charge trapping and reliability characteristics of sputtered Y2O3 high-k dielectrics on N- and S-passivated germanium

We demonstrate the potential of sulfur passivation to improve the interface characteristics between germanium (Ge) and Y2O3 high-k gate dielectric. Effects of nitrogen (N) and sulfur (S) passivation of the Ge surface on the charge trapping and reliability properties of Y2O3/Ge gate stacks are studied in detail and the results are compared. Sulfur passivation of the Ge surface has been performed using both the wet sulfidation technique with aqueous ammonium sulfide and plasma sulfidation with H2S gas. N-passivation of Ge substrates has been performed in NO plasma for comparison. Ultrathin (∼15 nm) Y2O3 films are deposited on both the N- and S-passivated p-Ge (1 0 0) wafers. Y2O3 films on the S-passivated Ge surface show low fixed oxide charge and interface state density than what is achieved with N-passivation. The electrical characterization results of MOS capacitors with Y2O3 films reveal the potential of S-passivation for the fabrication of Y2O3/Ge gate stacks for Ge MOSFETs.

P-Channel Ge MOSFET by Selectively Heteroepitaxially Grown Ge on Si

We successfully demonstrate Ge pMOSFET integrated on Si. In this process, Ge is grown selectively on Si on patterned SiO2 by heteroepitaxy, and pMOSFET is fabricated with gate dielectric stack consisting of thin GeO2 and Al2O3 and Al metal gate electrode. Fabricated devices show ~80% enhancement over the Si universal hole mobility. These results are promising toward monolithically integrating Ge MOSFETs with Si CMOS VLSI platform.

Interfacial Control and Electrical Properties of Ge MOS structures

Ge MOSFETs have generated a strong interest as a current drive enhancement technology beyond strained-Si technologies. The key technologies for realizing Ge MOSFETs are the formation of superior MOS interfaces. However, control technologies of to provide superior Ge MOS/MIS interfaces has not been fully established yet. In this report we review recent technologies for controlling Ge MOS interfaces. In particular, we report the interface properties of thermally-oxidized GeO2/Ge and Si-passivated GeO2 interfaces in detail. In addition, we introduce a new measurement method for studying the physical origin of low current drive in Ge n-MOSFETs, where electron and hole mobility of SiO2/Ge interfaces are evaluated for an identical MOS interface by using metal source/drain GOI MOSFETs with a Kelvin pattern.

SOI as Platform for Transition from Micro to Nano

Silicon On Insulator (SOI)-based devices seem to be the best candidates for the ultimate integration of ICs on silicon. The performance and physical mechanisms are addressed in single- and multi-gate thin film Si, Ge and III-V MOSFETs. The impact of tensile or compressive uniaxial and biaxial strains in the channel, of high k materials and metal gates as well as metallic Schottky source-drain architectures are discussed. The interest of SOI-based emerging and beyond-CMOS nanodevices for long term applications, based on nanowires, carbon electronics or small slope switch structures is presented. Finally, the possible 3D integration of multi-channels and stacked nanowires is also shown.