Ge MOSFETs Research Articles

Passivation of Ge/high-κ interface using RF Plasma nitridation

In this paper, plasma nitridation of a germanium surface using NH3 and N2 gases is performed with a standard RF-PECVD method at a substrate temperature of 250 °C. The structural and optical properties of the Ge surface have been investigated using Atomic Force Microscopy (AFM), Fourier Transform Infrared Spectroscopy (FT-IR), and Variable Angle Spectroscopic Ellipsometery (VASE). Study of the Ge (100) surface revealed that it is nitrated after plasma treatment while the GeO2 regrowth on the surface has been suppressed. Also, stability of the treated surface under air exposure is observed, where all the measurements were performed at room ambient. The electrical characteristics of fabricated Al/Ti/HfO2/GeON/p-Ge capacitors using the proposed surface treatment technique have been investigated. The C-V curves indicated a negligible hysteresis compared to ∼500 mV observed in untreated samples. Additionally, the C-V characteristic is used to extract the high-κ/Ge interface trap density using the most commonly used methods in determining the interface traps. The discussion includes the Dit calculation from the high-low frequency (Castagné–Vapaille) method and Terman (high-frequency) method. The high-low frequency method indicated a low interface trap density of ∼2.5 × 1011 eV−1.cm−2 compared to the Terman method. The J-V measurements revealed more than two orders of magnitude reduction of the gate leakage. This improved Ge interface quality is a promising low-temperature technique for fabricating high-performance Ge MOSFETs.

A Stress Response Model for Hole Mobility in the Inversion Layer of Ge MOSFETs

A Stress Response Model for Hole Mobility in the Inversion Layer of Ge MOSFETs

Investigation of Border Trap Characteristics in the AlON/GeO2/Ge Gate Stacks

Aluminum oxynitride (AlON) is investigated as a germanium oxide (GeO) desorption barrier layer for Ge MOSFETs. Interface and border traps in the AlON/GeO2/Ge gate-stack are discussed in detail and compared with those in the Al2O3/GeO2/Ge gate-stack via MOS and MOSFET structures. Although the interface traps remain the same for AlON and Al2O3 in the gate stacks, the AlON gate-stack exhibits a reduced border trap, which results in improved reliability over the Al2O3 gate-stack. This is supported by both the charge-trapping and low-frequency noise analyses.

Strain Engineering for Germanium-on-Insulator Mobility Enhancement with Phase Change Liner Stressors**Supported by the National Natural Science Foundation of China under Grant Nos 61376097, 61504120, and U1609213, the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001, and the Specialized Research Fund for the Doctoral Program of Higher Education of China under Grant No 20130091110025.

We investigate the strain in various Ge-on-insulator (GeOI) micro-structures induced by three phase-change materials (PCMs) (Ge2Sb2Te5, Sb2Te3, GeTe) deposited. The PCMs could change the phase from amorphous state to polycrystalline state with a low temperature thermal annealing, resulting in an intrinsic contraction in the PCM films. Raman spectroscopy analysis is performed to compare the strain induced in the GeOI micro-structures by various PCMs. By comparison, Sb2Te3 could induce the largest amount of tensile strain in the GeOI micro-structures after the low temperature annealing. Based on the strain calculated from the Raman peak shifts, finite element numerical simulation is performed to calculate the strain-induced electron mobility enhancement for Ge n-MOSFETs with PCM liner stressors. With the adoption of Sb2Te3 liner stressor, 22% electron mobility enhancement at could be achieved, suggesting that PCM especially Sb2Te3 liner stressor is a promising technique for the performance enhancement of Ge MOSFETs.

(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable. In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected. For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12]. We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds. For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices. This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.

Experimental Investigation of Ballistic Carrier Transport for Sub-100-nm Ge n-MOSFETs

We demonstrate an experimental study on the ballistic transport behavior of sub-100 nm GeOI n-MOSFETs, by adopting an ultrafast pulsed I–V system for measurement. High performance GeOI n-MOSFETs suffer severer self-heating effect and traps in the dc characterization process than in a “real” high-speed IC circuit. In this letter, the ballistic transport parameters for nanoscale Ge n-MOSFETs are extracted by the pulsed I–V method, and is compared with the SOI n-MOSFETs. The ballsiticity for Ge MOSFETs is higher than Si transistors at the same gate length ${L}_{\text {G}}$ . Furthermore, the scalability of the ballistic parameters for Ge n-MOSFETs is modeled and predicted for the sub-10-nm technology nodes.

(Invited) Significant Reduction of Leakage Currents in Reverse-Biased Ge n+/p Junctions by Taking Care of Peripheral Passivation Layer

Drastic enhancement of electron mobility and deep understanding of carrier transport in Ge MOSFETs have been made thanks to a significant reduction of major extrinsic carrier scattering sources such as Dit [1] and surface roughness [2]. Furthermore, EOT scaling in Ge gate stacks [3] in addition to the gate stack reliability [4] have also been demonstrated. One of the remaining big challenges in Ge MOSFETs is rather high leakage currents at n+/p junctions. We recently found that oxygen atoms in Ge substrate have an appreciable effect on reverse-biased n+/p junction leakage current. This result is good news for Ge technology [5]. In this presentation, we discuss the leakage current mechanism in Ge n+/p junctions. We prepared n+/p junctions with various areas, and investigated the dependence of the leakage currents both on area and perimeter length, by changing the peripheral passivation layer. We found a dramatic effect of the passivation layer on the reverse-biased junction leakage current. By taking care of the passivation layer, we demonstrate more than 106 magnitude difference in the on/off ratio at n+/p junctions biased at V=|1| V , which is, to our knowledge, the highest ratio in the conventional planar n+/p junctions. It is true that the junction leakage is intrinsically poor in Ge due to a narrower energy band gap, but this paper strongly suggests that the poor quality of Ge n+/p junctions fabricated in the current technology is not intrinsic but quite process and materials dependent. Thus, it is expected that Ge CMOS technology including junction leakage current will be further improved by detailed understanding of Ge properties. [1] C. H. Lee et al., IEEE TED-58(2011) 1295. [2] T. Nishimura et al., Appl. Phys. Exp. 5(2012) 121301. [3] C. Lu et al., Dig. VLSI Tech. Symp. (2015) 2.4. [4] C. Lu et al., Tech. Dig. IEDM (2015). 14.6. [5] A. Toriumi et al., ECS-T, 69(5) 287 (2015).

Selected Success Stories from Twenty Years of High-k Gate Dielectric Research

There are many success stories from the high-k gate dielectric research, carried out during the last two decades or so (say, 1996 to 2016), only a few of which could be accommodated in this paper. We plan to highlight four successful enterprises, namely, (1) Atomic Layer Deposition (ALD) of HfO2 (including HfON, HfSiON), (2) Enhancement of the dielectric constant k through structural transformation and/or compound formation, (3) Role of the SiO2/high-k Interface Dipole and the Cap Layer at the high-k/metal interface in controlling the flat-band voltage, (4) Passivation of the Ge surface and Ge MOSFET with high channel mobility. These topics will be analyzed critically and the underlying physics will be presented. Atomic Layer Deposition scores over competitors (MOCVD, Magnetron Sputtering) in terms of better film uniformity and conformity (against uneven surfaces) with less pinhole. The alkyl-amide precursors: (TDMAH - Hf[N(CH3)2]4), (TEMAH - Hf[N(C2H5) (CH3)]4), (TDEAH - Hf[N(C2H5)2]4) were found to be suitable for low temperature deposition of smooth (RMS roughness ca. 1% of film thickness), uniform (thickness and composition wise), dense (ρ = 9.23 gcm-3, i.e. 95% of the density of the monoclinic phase), low contamination (< 1% C and < 0.25% N), and conformal (100% site coverage on holes with > 35 aspect ration) films of HfO2 with a deposition rate of ca. 0.093 nm per cycle.ALD is claimed to be a self-limiting process, but it was found that self limiting surface reaction occurred at a particular precursor temperature corresponding to a specific precursor dose; these precursor temperatures for the saturating dose were 75, 115, and 130 oC for TDMAH, TEMAH, and TDEAH, respectively. High deposition temperatures culminated in precursor decomposition followed by non-uniform films or no deposition on the substrate; moreover, HfO2 film surface roughness increased due to growth of crystallites. One main concern is the contamination of the deposited high-k layer by the chemical reaction by-products – generally C, Cl, N, and H. Post-deposition O3 treatment can reduce C, H contamination by producing H2O, CO or CO2 followed by their out-diffusion. Higher deposition temperature results in lower C contamination. High temperature annealing between ALD stages has been found to lower the C contamination; likewise has been NH3/Ar plasma treatment. Typically, the value of the dielectric constant k for a high-k alloy varies in a monotonous (somewhat linear) fashion as a function of the mixing ratio between those of the two components of a binary alloy. Departure from the above trend can happen, as experiments suggest, if a major structural transformation of the alloy matrix takes place. HfO2 can occur in three crystal structures – monoclinic, cubic, and tetragonal – with different values of permittivity. The cubic and the tetragonal HfO2 have higher dielectric constant k (from theory – 29 and 70 respectively) than the monoclinic polymorph. Permittivity is determined by the ratio αm/Vm, where αm is the molar polarization and Vm is the molar volume. Analysis suggests that a reduced molar volume may be mainly responsible for the larger k value of the cubic and tetragonal HfO2. Unfortunately, at room temperature and up to about 1750 oC, the stable phase of HfO2 is monoclinic - one with the lowest value of k among the polymorphs. The option therefore lies in finding phase modifiers, which can transform the low-k to the high-k phase and stabilize that phase in the temperature range the MOSFET is subjected to during processing. Experiments have revealed the ability of some dopants, e.g. Y, Si, La, Gd, Er, Dy, Sc, Ce, to be effective phase modifiers of HfO2. An interface dipole refers to an electrical bilayer of equal and opposite charges located within atomic distance on each side of an interface; as the electric field in the interface dipole will have a Dirac delta form, it will be represented by an interface dipole potential, which has no dependence on the physical thickness. There exists strong evidence to indicate that a dipole is present across the IL/high-k interface, when the IL is an SiO2 layer. Elements of the SiO2/high-k interface dipole model have been affirmed by the results of many investigations. Perhaps, its strongest support comes from the wide technological use of a capping layer in high-k MOSFET manufacturing to control and adjust the threshold voltage. The experimental data reported by many investigators appear to suggest that the SiO2/high-k interface dipole is the dominant entity controlling the flat-band voltage VFB.

Impact of N2O/NH3/N2 Gas Mixture on the Interface Quality of Germanium MOS Capacitors

The development of high quality germanium based devices has been generating a lot of interest due to the excellent optical and electrical properties of germanium [1-4]. From an optical perspective germanium has high index of refraction, low optical dispersion, and the possibility to tune the silicon physical properties and reduce the band gap by controlling Ge content which makes it very useful for photo-detectors application. Furthermore, the bulk hole and electron mobility of Ge are approximately four and two times higher than conventional Si channel, respectively, which makes it an excellent candidate for future high performance complementary metal-oxide-semiconductor (CMOS) devices. The major weaknesses in Ge technology is germanium oxide (GeO and GeO2) stability and water solubility, the poor quality of Ge/ high κ-dielectric interfaces and the difficulty in forming a low-Dit (density of traps) Ge metal-oxide-semiconductor interface. However, a superior high-k/Ge gate stack satisfying low Dit and thin EOT simultaneously is mandatory for high performance Ge-channel devices. Several techniques have been adopted for Ge interface passivation, among them the oxygen-based passivation such as GeOx which has been proved to be thermally unstable, while nitrogen-based passivation has better thermal stability. Furthermore, the energy needed to break the nitrogen-oxygen bond is smaller than that of oxygen-oxygen bond in O2 plasma which makes nitration-based passivation a low temperature technique and compatible with Ge MOSFET fabrication. In this paper a mixture of N2O, NH3 and N2passivation on Ge is performed using RF-PECVD reactor and extensively studied in terms of Ge MOS capacitor. In order to fabricate Ge MOS capacitor a P-type (100) Ge substrate with a resistivity of (5-10) mΩ.cm is cleaned by diluted 1:10 BHF solution. After being cleaned the samples is loaded immediately to an Oxford Instruments System 100 PECVD tool at RF frequency of 13.56MHz.The plasma power was fixed at 20W and a 710 sccm flow of N2O for 2min is used in all treated samples as a pre plasma clean step. After this 380 sccm of N2 and 30 sccm of NH3 were performed at 285 ºC and pressure of 1T at different exposure time on top of the Ge surface. A sample without passivation is fabricated as a control sample. A 5nm thin film of HfO2 was deposited by plasma- Atomic Layer Deposition (ALD) at 200 ºC, followed by Al deposition using e-beam evaporator through a shadow mask to define the gates. Finally, post dielectric annealing was carried out at 400 ºC for 10min under forming gases. Capacitance-Voltage (C-V) measurements are carried out using Agilent B 1505 A curve tracer + Signatone manual 1160 prober. Fig. 1 shows a schematic of the fabricated gate stack and Fig. 2 shows the typical C–V characteristics of nMOS capacitors without (a) and (b), (c) and (d) with N2O/NH3/N2 treatment at different exposure time. As can be seen from Fig.2 the hump is invisible for the samples passivated by N2O/NH3/N2, indicating that the formed GeOxNy IL may block the impurities from diffusing from the gate dielectric into the Ge substrate. Furthermore, the hysteresis of metal–oxide–semiconductor (MOS) capacitor with HfO2 serving as gate dielectric is reduced to ~150 mV, compared with ~400mV mV of the untreated one. Moreover, this passivation technique can act as an effective method for high performance NMOSFET devices. 1. R.Cariou, R.Ruggeri, X.Tan, Giovanni Mannino, J.Nassar, and P.Roca I Cabarrocas, structural properties of relaxed thin film germanium layers grown by low temperature RF-PECVD epitaxy on Si and Ge (100) substrate, AIP Advances 4,077103 (2014). 2. Ammar Nayfeh, Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si, IEEE ELECTRON DEVICE LETTERS, 26 (9), 2005. 3. Ali K Okyay, Ammar M Nayfeh, Krishna C Saraswat, Takao Yonehara, Ann Marshall, Paul C McIntyre, High-efficiency metal–semiconductor–metal photodetectors on heteroepitaxially grown Ge on Si, Optics Letter, 31(17), 2006. 4. Mahmoud S Rasras, Douglas M Gill, Mark P Earnshaw, Christopher R Doerr, Joseph S Weiner, Cristian Bolle, Young-Kai Chen, CMOS silicon receiver integrated with Ge detector and reconfigurable optical filter,IEEE photonic Technology Letters, 22(2), 2010. Figure 1

Ge GAA FETs and TMD FinFETs for the Applications Beyond Si—A Review

Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal, the defect-free Ge channel can be formed on nothing. The ${p}$ -channel triangular Ge GAA FET with fin width ( ${W} _{\mathrm{ fin}}$ ) of 52 nm and Lg of 183 nm has $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}} = 10^{5}$ , SS = 130 mV/dec, and Ion = 235 $\mu \text{A}/\mu \text{m}$ at -1 V. Next, due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the $n$ -channel triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced Ion with respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can be further improved if superior gate stack than EOT = 5.5 nm and Dit $= 1\times 10^{12}$ cm $^{-2} \cdot $ eV $^{-1}$ is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defect-free suspended channel, nFET and pFET with excellent performance have been demonstrated, including an $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ratio exceeding $10^{8}$ , the highest ever reported for Ge-based pFETs. The TMD FinFET devices are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS2 covered on Si fin and nanowire resulted in improved (+25%) $\text{I}_{on}$ of the FinFET and nanowire FET. The PFETs also operated effectively and the N/P device $\text{V}_{\mathrm{ th}}$ are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide enables 0.5 V of $\text{V}_{\mathrm{ th}}$ shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

Impact of N2O/NH3/N2 Gas Mixture on the Interface Quality of Germanium MOS Capacitors

In this paper, nitration of germanium surface using a mixture of N2O, NH3 and N2 is performed using RF-PECVD reactor. The electrical characteristics of Al/HfO2/GeON/p-Ge capacitors are investigated. Results show that the hysteresis of metal–oxide–semiconductor (MOS) capacitors with nitration-based passivation step is reduced to ~150 mV, compared with ~400mV of the untreated sample. The suppression of hysteresis is attributed to the reduction of electron traps and enhancement of dielectric/Ge interface quality. The improved interface quality of plasma-based nitration of Ge surface is a promising technique for high performance Ge MOSFET fabrication.

Novel BF+Implantation for High Performance Ge pMOSFETs

BF+ implantation is used for the first time for the formation of source/drain (S/D) junctions in Ge MOSFETs. It offers a higher B activation level ( $\sim 2.0\times 10^{20}$ cm $^{-3})$ and a shallower junction depth in Ge compared with B+ and BF2+ implantation for the same projected range, after rapid thermal annealing at 800 °C. Germanium pMOSFETs using BF+ implantation demonstrate a high ON/OFF ratio of $\sim 10^{7}$ and an enhancement of ON current, due to the reduction of S/D series resistance compared with B+ or BF2+ implanted junctions.

Electrical Effects of a Single Extended Defect in MOSFETs

The electrostatic and leakage effects of extended defects on Si and Ge MOSFETs are investigated. A technology computer-aided design model of extended defects is developed based upon measured device electrical properties. A single extended defect is introduced into simulated 2-D planar and 3-D FinFET structures. It is found that a 2-D extended defect is a source of variability in planar transistors, with the electrical effects depending on its position along the channel. A 2-D extended defect increases the threshold voltage and subthreshold swing when it is in the channel and increases the leakage current when it is in the drain. The dislocation effect on transistor characteristics increases with decreasing transistor width. The effect is less pronounced in FinFETs due to the well-controlled electrostatics and the small dislocation volume.

A Study on Contact Resistance Reduction in Ni Germanide/Ge using Sb Interlayer

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

Development of a methodology for the extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs and estimation of analog circuit performance

We have developed an algorithm which utilizes model equations for MOSFETs to extract BSIM3v3.2.2 MOSFET model parameters of Ge-channel transistors. The model represents the entire transfer characteristics from sub-threshold to strong inversion regions and the output characteristics from linear to saturation regions thus capturing all the operating bias conditions of gate to source voltage VGS and drain to source voltage VDS. For extraction of various BSIM parameters, the model equations are fitted with reported experimental characteristics, and some with TCAD simulation data of Ge MOSFETs for various geometrical dimensions over a wide range of bias conditions. The algorithm used for extracting BSIM3V3.2.2 parameters by fitting BSIM3v3.2.2 model equations with experimental or simulation data is written in MATLAB code. The extracted BSIM model parameters are employed in ADS circuit simulator to reproduce the transfer characteristics of Ge MOSFETs with the same channel length and channel width of 80 nm for both high and low body bias conditions. The characteristics obtained from ADS match well with those obtained from TCAD simulation using SILVACOATLAS thereby ensuring the accuracy of our extraction methodology. The extracted set of BSIM3V3.2.2 parameters is used to generate transfer and output characteristics of Ge channel pMOSFETs at channel length of 70 nm. The extracted value of threshold voltage, bulk mobility and saturation velocity are −0.2 V, 0.18 m2/V.s and 1.2 × 106 m/s, respectively. Our study reveals that various device parameters such as transconductance, intrinsic voltage gain, and cut-off frequency show a maximum value of 677 μS/μm, 2.7, and 63 GHz, respectively.

High-performance germanium n+/p junction by nickel-induced dopant activation of implanted phosphorus at low temperature**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176092 and 61474094), the National Basic Research Program of China (Grant Nos. 2012CB933503 and 2013CB632103), and the National Natural Science Foundation of China–National Research Foundation of Korea Joint Research Project (Grant No. 11311140251).

High-performance Ge n+/p junctions were fabricated at a low formation temperature from 325 °C to 400 °C with a metal(nickel)-induced dopant activation technique. The obtained NiGe electroded Ge n+/p junction has a rectification ratio of 5.6× 104 and a forward current of 387 A/cm2 at −1 V bias. The Ni-based metal-induced dopant activation technique is expected to meet the requirement of the shallow junction of Ge MOSFET.

Formation of Low-Resistivity Metal/Germanium Contact with Ultra-Thin Interlayer and Plasma Oxidation for n-Channel Germanium FET

Germanium (Ge) has emerged as a new channel material substituting traditional silicon (Si) in CMOS technology due to its high carrier mobility and process compatibility with Si. However, n-channel Ge MOSFET has not exhibited high performance because of some bottlenecks. High source/drain (S/D) contact resistance resulted from Fermi-level pinning (FLP) between the metal and Ge is the most serious obstacle for the development of Ge n-MOSFET. The metal/n-Ge contact has very large Schottky barrier height, approximately 0.55eV, regardless of metal work function because the Fermi-level on the metal side is strongly pinned to the edge of the valence band of Ge. Metal-induced gap states (MIGS) are the main cause of Fermi-level pinning, however, effect of interface states at the Ge surface on FLP is turned out to be not small by previous researches [1, 2]. Therefore, it is important to reduce both MIGS and interface states in order to alleviate FLP and form low-resistance Ge S/D contact. In this work, moderately-doped n-Ge wafer (N d = 1×1017 cm–3) was used as a substrate. In order to alleviate FLP of metal/n-Ge contact, 1.5 nm-thick ultra-thin TiO2 layer is inserted between the metal and n-Ge to block MIGS penetration into the energy gap of Ge, and plasma oxidation process is introduced before and after TiO2 deposition, respectively, to passivate Ge surface and reduce interface states [3]. Two approaches of plasma oxidation are applied; pre-oxidation and post-oxidation. The plasma oxidation process was carried out using ICP-RIE system. For pre-oxidation process, Ge substrate was oxidized prior to the TiO2 deposition with source power of 500 W, no bias power, gas flow of O2 40 sccm/Ar 5 sccm, pressure of 10 mTorr, and process time of 70 sec. For post-oxidation process, Ge substrate was oxidized after the TiO2 deposition with bias power of 50 W and process time of 30 sec with other plasma conditions not changed. The TiO2interlayer was deposited using atomic layer deposition (ALD) system at process temperature of 250 °C. As a result, a back-to-back reverse current density of Ti/TiO2/GeOx/n-Ge structure is improved compared to that of Ti/TiO2/n-Ge structure for both pre-oxidation and post-oxidation as shown in Fig. 1, which means Fermi-level on the metal side was more unpinned due to the GeOx passivation layer. It exhibits 4 orders of magnitude of reverse current improvement than the Ti/n-Ge structure does. Besides, the TiO2/GeOx stack shows better electrical properties than single TiO2 does when they have the same total thickness, approximately 2.1 nm (not shown here). It means an increase of single interlayer thickness in metal-interlayer-semiconductor (M-I-S) structure cannot be the best solution for FLP, and multi-layered structure should be introduced to reduce both MIGS and interface states. The Ti/TiO2/pre-GeOx/n-Ge shows slightly better performance than the Ti/TiO2/post-GeOx/n-Ge does. This is because the amount of GeOx formed by post-plasma oxidation process is smaller than that formed by pre-oxidation process due to the presence of TiO2 interlayer as shown in Fig. 2. Thicker GeOx can block MIGS more resulting in slight increase of reverse current density, however, GeOx layer formed by post-oxidation process has more GeO2-like characteristics which can passivate Ge surface better. For this reason, the Ti/TiO2/post-GeOx/n-Ge structure exhibits more ohmic-like (i.e., more linear) I–V characteristics, and post-oxidation process is considered to have more potential to plasma passivation process for the M-I-S structure. In conclusion, we successfully demonstrate the effect of pre- and post-oxidation process on Ge M-I-S structure. The GeOx layer formed by plasma oxidation between the metal and the TiO2 interlayer can reduce interface state density resulting in additional Fermi-level unpinning. Therefore, this plasma oxidation process with M-I-S structure can be a key technology to overcome the bottleneck of Ge n-channel MOSFET development by alleviating FLP effectively and reducing S/D contact resistance. [1] G.-S. Kim et al., IEEE Electron Device Lett., 36, 8 (2015) [2] J.-R. Wu et al., Appl. Phys. Lett., 99, 25 (2011) [3] J. Kang et al., Opt. Express, 23, 13 (2015) Figure 1

Enhancing Thermal Stability of Nickel-Germanide Alloy up to 600 °C By Using Metal Passivation

I. Background/ Objectives For continuous MOSFET scaling, Ge is one of the most promising candidates due to its higher mobility than Si. But, Ge has lower activated carrier concentration that will induce larger source/drain resistance because of lower sloid solubility and density of state. Hence, metal source/drain with remarkably low resistance is attractive for high performance Ge MOSFET. Even so, poor thermal stability of alloy is a critical problem in process integration. In the previous studies [1]-[3], Ni Germanide (NiGe) shows an enough low resistivity, low formation temperature and feasibility for self-aligned fabrication. However, NiGe through high temperature (>500 °C) show a fatal agglomeration phenomenon that badly degrades the junction performance. In this study, we successfully demonstrate that NiGe with Ti or TiN passivation can suppress the degradation of NiGe alloy and depict excellent thermal stability up to 600 °C. An on/off current ratio of approximately 4x105and low leakage current are shown for the NiGe contact with covering Ti and/or TiN are obtained by 600 °C alloy formation. II. Experiment Details Fig. 1 shows the process flow and device structure. n-Ge (100) substrates with a resistivity of 0.04 ~ 0.6 Ω-cm were cleaned by cyclic diluted HF (1:20) and DI water to remove the native oxide. After the clean process, a 420 nm SiO2 film was first deposited by plasma-enhanced chemical vapor deposition (PECVD) for isolation. The contact window was defined by using photolithography, and the subsequent oxide etch was accomplished by using a buffer oxide etchant (BOE). Multi-layer metal deposition was accomplished without reaking the vacuum in sputter chamber, and metal lift-off process was performed. Post-deposition annealing (PDA) conditions at 200/300/400/500/600 °C were employed for 60 s in N2ambient by rapid thermal annealing (RTA). Finally, the metal electrodes were carried out by metal sputter. III. Experiment Results Fig. 2(a) shows the I-V characteristics for all junctions formed 600 °C. We find that NiGe without cover shows serious agglomeration, which can be clearly observed by the Atomic Force Microscopy (AFM) image shown in the insert of Fig. 2(a). Compared to the Ni case, Ni/TiN or Ni/Ti/TiN cases show no degradation in off-current and enhanced on-current up to near one order of magnitude. Fig. 2(b) shows the electrical characteristics of on-/off-current for varied PDA conditions. Ni case is obviously degraded as the temperature increases. Compared to Ni case, Ni/TiN and Ni/Ti/TiN cases can successfully suppress the junction leakage and improve the thermal stability of NiGe. The electrical data reveal that Ni/Ti/TiN contact with 600 °C PDA shows the best on-current (approximately 4.4x102 A/cm2) and off-current (approximately 1x10-3 A/cm2). On-off ratio of Ni case is only of approximately 3x102, but Ni/TiN and Ni/Ti/TiN cases are of approximately 4x105. The current ratio can get the three orders enhancement on high temperature annealing at 600 °C. Fig. 3 shows the X-ray Photoelectron Spectroscopy (XPS) spectra of the Ni/Ti/TiN case, and we can see Ni has already diffused into Ge but Ti show much less diffusion. So, the junction is still a NiGe/Ge one. IV. Conclusions In summary, we have successfully eased the high temperature degradation for NiGe by using TiN or Ti metal passivation. The high on-off current ratio (approximately 4x105) was arrived by performing Ti/TiN on Ni under high temperature. It is very straightforward to extend the NiGe application and enlarge the process window for high performance Ge device.

Improved Electrical Characteristics of Ge pMOSFETs With ZrO2/HfO2Stack Gate Dielectric

Electrical characteristics of Ge pMOSFETs with HfO2, ZrO2, ZrO2/HfO2, and HfZrO x gate dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in ZrO2 device, which, however, has a higher interface trap density ( $\text{D}_{\mathrm { {it}}})$ due to its inferior dielectric/Ge interface. Interestingly, the $\text{D}_{\mathrm {{it}}}$ and sub-threshold swing of Ge pMOSFETs are clearly reduced by ZrO2/HfO2 stack gate dielectric. A peak hole mobility of 335 cm+ $^{{{2}}}$ /V-s is achieved in ZrO2/HfO2 device thanks to good dielectric/Ge interface. Furthermore, the EOT of ZrO2/HfO2 device is 0.62 nm, and the leakage current is $2\times 10^{{ {-3}}}$ A/cm $^{{{2}}}$ . Therefore, a ZrO2/HfO2 stack gate dielectric is promising for Ge MOSFETs.

(Invited) Effects of Ge Substrate Annealing in H2 on Electron Mobility as well as on Junction Leakage in n-channel Ge MOSFETs

This paper discusses H2 annealing effect of Ge substrate on carrier mobility and junction leakage current in Ge MOSFETs. We found that H2 annealing of Ge wafer improved the electron mobility in Ge n-channel MOSFETs, while it degrades n+/p junction leakage current. Although we have not clarified the mechanisms causing such significant effects, we have found that the oxygen content in Ge surface region is phenomenologically related to above effects of Ge in H2 annealing.