Abstract

Drastic enhancement of electron mobility and deep understanding of carrier transport in Ge MOSFETs have been made thanks to a significant reduction of major extrinsic carrier scattering sources such as Dit [1] and surface roughness [2]. Furthermore, EOT scaling in Ge gate stacks [3] in addition to the gate stack reliability [4] have also been demonstrated. One of the remaining big challenges in Ge MOSFETs is rather high leakage currents at n+/p junctions. We recently found that oxygen atoms in Ge substrate have an appreciable effect on reverse-biased n+/p junction leakage current. This result is good news for Ge technology [5]. In this presentation, we discuss the leakage current mechanism in Ge n+/p junctions. We prepared n+/p junctions with various areas, and investigated the dependence of the leakage currents both on area and perimeter length, by changing the peripheral passivation layer. We found a dramatic effect of the passivation layer on the reverse-biased junction leakage current. By taking care of the passivation layer, we demonstrate more than 106 magnitude difference in the on/off ratio at n+/p junctions biased at V=|1| V , which is, to our knowledge, the highest ratio in the conventional planar n+/p junctions. It is true that the junction leakage is intrinsically poor in Ge due to a narrower energy band gap, but this paper strongly suggests that the poor quality of Ge n+/p junctions fabricated in the current technology is not intrinsic but quite process and materials dependent. Thus, it is expected that Ge CMOS technology including junction leakage current will be further improved by detailed understanding of Ge properties. [1] C. H. Lee et al., IEEE TED-58(2011) 1295. [2] T. Nishimura et al., Appl. Phys. Exp. 5(2012) 121301. [3] C. Lu et al., Dig. VLSI Tech. Symp. (2015) 2.4. [4] C. Lu et al., Tech. Dig. IEDM (2015). 14.6. [5] A. Toriumi et al., ECS-T, 69(5) 287 (2015).

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