Gate Tunnel Field Effect Transistor Research Articles

ANALYTICAL MODELLING AND SIMULATION OF TRIPLE MATERIALS DOUBLE GATE GERMANIUM SOURCE FERROELECTRIC TUNNEL FET FORLOW POWER APPLICATIONS

At the nanoscale, many multigate devices are being studied in order to reduce their size and improve their performance. This paper describes the design and development of a novel device known as the Triple Material Surrounding Gate Tunnel Field Effect Transistor (TMSGTFET). The advantages of encircling gate and tunnel FET are combined to build a novel structure. The gate material around the device is replaced with three gate materials with various work functions to prevent short channel effects. The device's surface potential, lateral electric field, vertical electric field, and drain current are all modelled in two dimensions, with the results explained. By altering the thickness of the ferroelectric layer and ferroelectric material, as well as verifying the simulation findings with MATLAB, we study the impacts of device parameters on the channel potential and on-state current. The findings show that raising the ferroelectric layer thickness enhances the device's characteristics by reducing the shortest tunnelling length. Furthermore, the proposed analytical model shows increased ON current. CAD simulation is used to test the model's improved device properties, confirming that it is accurate

Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology

Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (< 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

A high performance trench gate tunneling field effect transistor based on quasi-broken gap energy band alignment heterojunction

In this letter, a tunneling field effect transistor based on quasi-broken gap energy band alignment (QB-TFET) is proposed and investigated by simulation method. To offering high on-state current, InGaAs/GaAsSb heterojunction with quasi-broken gap energy band alignment is applied to QB-TFET to improve the band-to-band tunneling rate. Trench gate structure and InGaAs pocket layer are applied to further increase the tunneling efficiency. To suppress the leakage current caused by the off-state tunneling path from source to drain, an intrinsic InGaAs spacer is inserted between n+ InGaAs drain and p+ GaAsSb source. In order to further improve the control ability of gate voltage on channel, TiO2 is used as the gate dielectric of the proposed QB-TFET. Moreover, the effect of x and y fraction of In x Ga1–x As and GaAs y Sb1–y on quasi-broken gap tunneling junction are studied in this work. The electrical characteristic change of QB-TFET with different x and y fraction is analyzed. The proposed QB-TFET is compared with other works and shows an obvious advantage on performance. As a result, a large on-state current (I on) of 921 μA μm−1 can be obtained. Moreover, steep average subthreshold swing (SSavg) of 4.9 mV/dec can be achieved when I on = 1 μA μm−1.

Analytical modeling of dielectrically modulated broken-gate tunnel FET biosensor considering partial hybridization effect

Currently Tunnel Field Effect Transistors (TFET) have picked up tremendous recognition in bio-sensing applications. Having a similar perspective, this paper proposes a preliminary novel channel centre potential based analytical model for broken gate TFET biosensor device. The model incorporates dielectric modulation and steric hindrance effects and demonstrates the effect of device parameter variations and partial hybridization in the nano-cavity on the sensitivity of the bio-sensor. Two types of fill profiles have been examined for sensitivity variation. The model shows good agreement with the real time TCAD simulation data and existing literature. Also, the model proves its robustness by responding in conditions of low channel occupancy (∼40%) and for biomolecules ranging from medical to industrial grade (high-K). The model is computationally intuitive and provides scope for application specific optimizations. The broken structure helps in reducing the ambipolarity without adversely affecting the sensitivity of the biosensor.

Design of Universal Logic Gates using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit.

Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).

Drain current model for a hetero‐dielectric single gate tunnel field effect transistor (HDSG TFET)

AbstractTunnel field effect transistor (TFET) is a potential candidate to replace CMOS in deep‐submicron region due to its lower SS (subthreshold swing, <60 mV/decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two shortcomings, a new structure, known as Hetero‐dielectric gate TFET (HDG TFET), has been proposed in the literature. To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the analytical current model for Hetero‐dielectric single gate (HDSG) TFET structure without using any iterative method. The developed analytical models show a good agreement with 2‐D TCAD simulator results. The model is used to study the electrical behavior of the proposed device under various physical and bias variations.

Analytical modeling of subband quantization and quantum transport in very Low-dimensional dual metal double gate TFET

We present a novel and comprehensive quantum analytical modeling of a sub-20 nm Dual Metal Double Gate (DMDG) Tunnel Field Effect Transistor (TFET) for the first time in literature. Owing to structural confinement at sub-20 nm regime, the energy states at channel are quantized and carrier propagation is regulated by quantum transport . We address such quantization aspects (viz. subband quantization, bandgap shifting, tunneling through barrier etc.) and incorporate them in analytical modeling using self-consistent solution of Schrödinger-Poisson's equation. As a result of work function difference at gate, we observe creation of quantum well , followed by a tunneling barrier, along the channel. Energy states in the quantum well are derived from Schrodinger equation, whereas, transmission coefficients are derived for each tunneling barrier. Finally, current density is obtained using ‘Landauer formula for quantum transport’. We methodically study the effects of structural confinement on device performances and observe significant shift from classical counterpart. Moreover, we note that quantization in DMDG TFET can be optimized that will lead to superior device performance. The results are verified with simulation data in each occasion to substantiate analytical models. • In this work, compact analytical model of quantum confinement in low-dimensional Dual Metal Double Gate TFET is presented. • Formation of quantum well, quantum tunneling, band gap widening effect and density of states correction are analysed. • Modelling is done based upon self-consistent Schrödinger-Poisson's solution and ‘Landauer formula for quantum transport’. • Device performances are explored in light of quantum confinement and results are validated through device simulation. • Comparative performance analysis is presented between semi-classical and quantum approach..

Improved Switching Performance of a Novel Auxiliary Gate Raised Dual Material Hetero-Dielectric Double Gate Tunnel Field Effect Transistor

Improved Switching Performance of a Novel Auxiliary Gate Raised Dual Material Hetero-Dielectric Double Gate Tunnel Field Effect Transistor

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

Performance Analysis of HfO2-SiO2 Stacked Oxide Quadruple Gate Tunnel Field Effect Transistor for Improved ON Current

Performance Analysis of HfO2-SiO2 Stacked Oxide Quadruple Gate Tunnel Field Effect Transistor for Improved ON Current

Boosting on Current Using Various Source Material for Dual Gate Tunnel Field Effect Transistor

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

A T-shaped gate tunneling field effect transistor with negative capacitance, super-steep subthreshold swing

With the development of semiconductor technology, the size of traditional metal oxide semiconductor field effect transistor devices continues to decrease, but it cannot meet the requirements of high performance and low power consumption. Low power tunneling field effect transistor (TFET) has gradually become the focus of researchers. This paper proposes a novel T-shaped gate TFET based on the silicon with the negative capacitance (NC-TGTFET). On the basis of TGTFET, ferroelectric material (HZO) is used as gate dielectric. The simulation results show that, compared with the traditional TGTFET, the opening order and sensitivity of the two tunneling junctions are different. The influences of thickness and the doping concentration of pocket and ferroelectric material properties on the characteristics of NC-TGTFET is also discussed by Sentaurus simulation tool. Furthermore, the negative capacitance of ferroelectric material makes NC-TGTFET have a very steep subthreshold swing (18.32 mV/dec) at the range of drain current from 1 × 10−15 to 1 × 10−7 A μm−1. And the on-state current (V g = 0.5 V, V d = 0.5 V) is 1.52 × 10−6 A μm−1.

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

This report investigates a novel dielectric pocket—pocket intrinsic triple gate tunnel field effect transistor to magnify a device’s performance well suited for low-power applications. The source engineering which was adopted here using DP and PI has resulted in improved drive current of the device. A heterojunction was also formed between low bandgap energy materials and silicon, at the source side, to escalate the carrier tunneling at the interface of source and channel. Gate-drain overlapping technique, usage of high bandgap materials in drain region along with high-K dielectric materials in oxides ensured low ambipolar current, low off current, and a steeper subthreshold slope respectively. With these traits, the proposed device is believed to be suitable for low-power applications. The proposed structure is simulated, and the electrical parameters are analysed using the SILVACO TCAD ATLAS tool.

A Charge Plasma Based Label Free Biomolecule Detector Using SiGe-Heterojunction Double Gate Tunnel FET

To overcome the random dopant fluctuations (RDFs) and high thermal budget problems faced by normally doped Tunnel Field Effect Transistor (TFET) devices, charge plasma SiGe-heterojunction double gate TFET is utilized to design a label free biosensor. The performance of proposed biosensor is analyzed for different values of dielectric constant (k), charge density (both positive and negative), gate work function and cavity dimensions. These parameters alter the electric properties of the biosensor which help in the detection process. Their effect on the drain current, electric field, surface potential, sub-threshold swing (SS), ION/IOFF ratio, and electron tunneling rate (ETR) of the device is also discussed. Furthermore, the drain current sensitivity of the proposed biosensor is analyzed and it is found that a maximum sensitivity of 1.13 × 1010 is obtained for dielectric constant k = 12. The proposed biosensor is implemented by carrying out two-dimensional device simulations using the Silvaco ATLAS tool.

A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance

In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel field effect transistors (DL-DG-TFETs) with Si0.5Ge0.5 and Si as source material. The CP methodology resolves the issues of random doping fluctuation and doping activation. The analog and RF performance has been investigated for both the proposed devices i.e. Si0.5Ge0.5 source DL-DG-TFET and Si-source DL-DG-TFET in terms of drive current, transconductance, cut-off frequency. In addition, the linearity and distortion analysis has been carried out for both the proposed devices with respect to higher order transconductance (gm2 and gm3), VIP2, IMD3, and HD2. The Si0.5Ge0.5 source DL-DG-TFET has better performance characteristics and reliability in compare to Si-source DL-DG-TFET owing to low energy bandgap material and higher mobility. The switching ratio obtained for Si0.5Ge0.5 source DL-DG-TFET is order of 5 × 1014 that makes it a suitable contender for low power applications.

Investigation of the Device Electrical Parameters for Homo and Hetero Junction Based TFETs

This paper presents the analytical approximation of device physics of heterojunction based double gate (DG) Tunnel field effect transistors (TFETs) in terms of potential distribution, electron density and electron barrier tunneling. In order to improve the device performance with respect to ON current (ION), DG TFET with gate-drain overlap is developed. An asymmetric gate oxide is introduced in the gate - drain overlap region and is compared to DG TFET. The device physics and its performance characteristics are studied by using various materials, such as Si, SiGe, InAs and GaSb. The simulated results are validated against the model values. DG TFETs with gate-drain overlap offers higher tunneling probability compared to DG TFETs. Also GaSb/Si based DG TFETs with gate-drain overlap shows good performance improvement by offering higher tunneling probability which in turn offers a higher ION of 1.15 mA/μm.

Tweaking the Performance of Dopingless Nano-TFET with Misaligned Sandwiched Dual-Gate Structure

While scaling down the devices it is important not to compromise with the performance. Scaling of tunnel devices shows better performance than Field Effect Transistors (FETs). Charge Plasma based Dopingless Double Gate Tunnel Field Effect Transistor (DLDGTFET) with its various misaligned configurations are designed, discussed and analyzed in the presented work. Silicon is preferred as a choice of material. For various misalignment configurations, initially, bottom gate is shifted towards the right, then it is shifted towards left and at last bottom and top, both gates are misplaced for analyzing the device parameters, analog parameters and linearity parameters. By misalignment, it is observed that either the bottom gate is misaligned towards the right or left or both gates are being misaligned, device performance degraded. The basic structure shows the higher drain current, better drive current among other structures such as 15 μA. whereas source underlapped (SU100) structure shows the better subthreshold slope such as 20 mV/decade. But SU100 has the least amount of drive current. In the subthreshold region, BM100 has the maximum value of transconductance gain factor i.e. 104 V−1. When the bottom gate is shifted towards right i.e. for drain overlapped structure it was observed that it shows better linearity parameters and can be considered for low noise and low voltage applications.

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain underlap and a metal drain. The device is designed to address two important issues of a conventional TFET, that is, the poor ON current (ION) and the presence of ambipolar conduction. In the proposed device, the use of Ge material for the source region and a dual dielectric gate oxide enhances the ION significantly and employing metallic drain and a gate-drain underlap fully suppresses the ambipolarity conduction. This can be attributed to the formation of a Schottky barrier at channel/drain interface. Two-dimensional (2D) calibrated simulation studies have been performed using the commercial TCAD device simulator. The results have shown that the ION has improved by almost ~3 orders whereas ambipolar current is completely suppressed in the proposed device in comparison to the conventional DG-TFET. Further, it has been found that the proposed device has a subthreshold slope (SS) of 35 mV/dec, ION of ~2×10−4 A/ μm and the ION to IOFF ratio (ION/IOFF) of ~1013. The proposed device performance can be improved further by optimizing various device parameters, like underlap length etc. A flow chart mentioning the key fabrication steps has also been proposed to fabricate the proposed device.

Performance Analysis on Effect of Variation in Oxide Material of Double Gate Tunnel Field Effect Transistor

In this paper structure of Double Gate Tunnel Field Effect Transistor work to increase the efficiency of the device performance of Tunnel Field Effect Transistors making it one of the potential candidates for small scale devices. The essential point of this research work is to consider the performance analysis of the structure. This work is accomplished with the assistance of tool Cogenda TCAD version 1.9.2. The designing of the device, simulation and correlation of results have been gotten on this tool. The section gives the stream of Research Methodology and clarifies the footsteps for Design and Simulation of Double Gate Tunnel Field Effect Transistor.