Abstract
The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.
Highlights
Due to technical limitations, full-text HTML conversion of this manuscript could not be completed
The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches
The impact of stacked gate oxide topology is studied in this paper by comparing the characteristics with unstacked gate oxide
Summary
Full-text HTML conversion of this manuscript could not be completed. ) Cochin University of Science and Technology School of Engineering https://orcid.org/0000-0003-1616- Cochin University of Science and Technology Jobymol Jacob
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