Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

Abstract

In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain underlap and a metal drain. The device is designed to address two important issues of a conventional TFET, that is, the poor ON current (ION) and the presence of ambipolar conduction. In the proposed device, the use of Ge material for the source region and a dual dielectric gate oxide enhances the ION significantly and employing metallic drain and a gate-drain underlap fully suppresses the ambipolarity conduction. This can be attributed to the formation of a Schottky barrier at channel/drain interface. Two-dimensional (2D) calibrated simulation studies have been performed using the commercial TCAD device simulator. The results have shown that the ION has improved by almost ~3 orders whereas ambipolar current is completely suppressed in the proposed device in comparison to the conventional DG-TFET. Further, it has been found that the proposed device has a subthreshold slope (SS) of 35 mV/dec, ION of ~2×10−4 A/ μm and the ION to IOFF ratio (ION/IOFF) of ~1013. The proposed device performance can be improved further by optimizing various device parameters, like underlap length etc. A flow chart mentioning the key fabrication steps has also been proposed to fabricate the proposed device.