Full Adder Circuit Research Articles

Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit

It is very important to detect and correct faults for ensuring the validity and reliability of these circuits. In this regard, a comparative study with related existing techniques is undertaken. Two techniques to achieve the testability of reversible circuits are introduced that have been improved in terms of quantum cost and fault coverage rate. Considering this aspect, the main focus of these techniques is on the efficient detection and location of faults with 100% accuracy. These techniques for fault detection in reversible circuit design, in addition to being able to produce the correct outputs, can also provide information for fault location that has already been done at a higher cost. Proposed approaches have been successfully tested for all types of SMGF, MMGF, PMGF, RGF, and SBF. In order to verify the functional correctness of the proposed scheme, it also has executed the testing over a reversible full adder circuit, and findings are checked. In the following, the proposed approach of reversible sequential circuits is presented for the first time so far. The cost metrics are evaluated for all the proposed designs and compared the estimated results against some existing design approaches of reversible circuits for better understanding.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Design and Analysis of CMOS Full Adder

This paper presents a comparative study of Complementary MOSFET (CMOS) full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units (DSP). In most of these systems the adder lies in the critical path that determines the overall speed of the system. Full adder is mainly used in VLSI devices like microprocessor for computational purposes. The proposed full adder cell has low power consumption, better area efficiency. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Our aim is to design and compare the full adder circuit in various technologies and compare their power capacity. By using the hybrid structure of NMOS and PMOS, we have implemented the circuit of full adder.

An 8-b Multiplier Using Single-Stage Full Adder Cell in Single-Flux-Quantum Circuit Technology

Single-flux-quantum (SFQ) circuits operate at higher frequencies with much lower power consumption when compared to their CMOS counterparts. Synchronous SFQ circuits require full path balancing by inserting D-Flipflops as needed, an operation that tends to greatly increase the number of gates in a circuit. To control this increase in the total number of gates, complex multi-input SFQ logic gates can be built and used to synthesize the circuits. In this work, a 1-b full adder is built with sum and carries as two individual single-stage SFQ gates. Both of the sum and the carry cells are demonstrated with their schematics and layouts. Postlayout simulation based on the extracted circuit parameters by InductEx is done by using JSIM and demonstrates the correct functionality of the proposed full adder design. Later, an 8-b signed multiplier using this newly designed single-stage full adder is implemented to illustrate the advantages of the new design. The structure and timing strategy of the multiplier as well as the simulation result are shown. In the end, circuits of different sizes are synthesized with the single-stage full adder circuit, and the results are discussed.

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications

Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules. The principal peculiarity of these hybrid logic style-based FA cells is that each module could be optimized individually to improve the circuit performance. A high-performance 1-bit hybrid FA cell is proposed with pass transistor logic and transmission gate logic in the present work. The proposed FA circuit is implemented using 20-transistors to achieve optimum performance. The proposed circuit is simulated in Cadence virtuoso tool by using 90-nm process CMOS technology. Comparison of the design matrices for the proposed 1-bit hybrid FA cell against the five different reported FA circuits is also carried out. The present study reported 13.01–54.93 % and 13.01–59.20 % improvement in terms of delay and power delay product (PDP), respectively, compared to other FA designs. The proposed circuit is also investigated in different supply voltages (0.6–1.5V). Furthermore, the FA circuit is verified in different process corner conditions to check the robustness.

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

Design of Low-Power and PVT-Aware Quaternary Adder Circuits Based on Virtual Source-CNTFET Model

Two new robust quaternary half adder (QHA) circuits (one single source and one multiple sources) are proposed in this work for low power applications. The proposed circuits are designed in hybrid fashion based on three types of quaternary inverter circuits and compared with recently proposed existing models in terms of number of supplies, power dissipation, delay, power-delay product (PDP) and transistor count through extensive simulations in Cadence Virtuoso platform using Stanford’s Virtual Source-Carbon Nanotube Field Effect Transistor (VS-CNTFET) model. The sensitivity of the circuits in response to process parameters, voltage and temperature (PVT) variations are also evaluated. The proposed circuit with multiple sources has the lowest values of 4.92 uW for power consumption and 0.124 fJ for PDP compared to all other designs. Simulation results also demonstrate better stability to PVT variation for both the proposed architectures with respect to power and PDP parameters. In order to evaluate the competency of the proposed QHAs, quaternary full adder (QFA) circuits are designed using the proposed QHAs and other relevant models. Extensive simulation data confirm that the proposed circuits outperform others in terms of power penalty.

A new approach to bypass wire crossing problem in QCA nano technology

PurposeThis study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them.Design/methodology/approachQuantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder.FindingsA new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit.Originality/valueIn this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

An all-optical equalizer SWAP gate (ESG)

A reversible logic gate differs from the conversational logic gate in many ways, such as equal number of input–output, its reverse operation and bijective input/output mapping. In this paper, a new class of 4 4 conservative-reversible logic gate named the equalizer SWAP gate (ESG) has been proposed. This gate is self-invertible and performs SWAP operation when two of its control inputs are logic either 0 or 1. The all-optical design of the ESG using a ‘semiconductor optical amplifier (SOA) assisted Sagnac interferometer’ with a counter-propagating signal passing through the SOA has been shown with a mathematical model in this paper. Quantum realization of the ESG has been carried out to construct its unitary matrix. Also, the matrix has been established through numerical simulation. Some complex reversible logic circuits, viz. n-bit XOR/XNOR, full-adder circuit, n-bit binary-to-gray and gray-to-binary conversion, using the ESG unit have also been shown. Simulated outputs, logical complexity, quantum realization, optical cost and delay of the proposed circuit have been analyzed, and are compared with other reversible logic gates.

Noise-harnessing single-electron circuit with symmetrical, simple pair circuit structure and application to full adder circuit

We designed a noise-harnessing single-electron (SE) memory (SEM) pair circuit. An SEM consists of a capacitor and a double tunnel junction in series. The SEM pair circuit has two SEMs connected with a coupling capacitor. The circuit has a hysteresis characteristic and a symmetrical structure, and it achieves a substantial noise-harnessing capability by incorporating the stochastic resonance. We also implemented a summing network to improve the circuit performance. To demonstrate its practical application, we designed a full adder with a very simple structure by using only the summed SEM pair circuit. Through Monte Carlo computer simulation, we confirmed that the full adder operates correctly under a high-temperature condition. Moreover, our circuit can also operate with variations in capacitance caused by manufacturing processes. These results indicate that our SEM pair circuit, which operates by overcoming the disadvantages of SE circuits, has numerous practical applications as a useful, functional nanodevice.

Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. The CMOS (complementary metal oxide semiconductor) Logic family is preferred for digital circuits due to its performance and impeccable noise margins over other families. However, in CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. The aim ofthis paper is to carry out work that is focused on reducing the power dissipation in circuits, which increases with down scaling of circuits. The experimental work is carried out on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional based CMOS circuit and PFAL based CMOS circuit. In comparison with the conventional CMOS based 2:1 multiplexer circuit, the designed PFAL based CMOS 2:1 multiplexer circuit has lesser power dissipation which is measured as 80.871 picoWatts as compared to conventional CMOS circuit which has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit has 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Hybrid memristor-CMOS implementation of logic gates design using LTSpice

In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

Dynamic Power Consumption In CMOS N Bit Full-Adder Circuit

This paper discusses power consumption in the full adder circuit using some fabrication technologies. Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed. In this paper, the effect of changing the number of bits on the power consumption and time delay of the full adder circuit will be observed and the effect of changing the technology size is going to be calculated. The results will show that there is a direct relationship between the number of bits and power.

Area and power delay product efficient level restored hybrid full adder (LR-HFA)

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Design and Implementation of Quantum half Adder and Full adder Using IBM Quantum Experience

Quantum machine learning is the combination of quantum computing and classical machine learning. It helps in solving the problems of one field to another field. Quantum computational power can be advantageous in handling huge data at a faster rate.In this regard, quantum computational power can be advantageous in handling such huge data at a faster rate. Classical machine learning is about trying to find patterns in data and using those patterns to predict future events. Quantum systems, on the other hand, produces typical patterns which are not producible by classical systems, thereby postulating that quantum computers may overtake classical computers on machine learning tasks. Hence the whole motivation in this work is on understanding and analysing the half adder and full adder circuit design using Quantum mechanics.

Accuracy-Adaptive Spintronic Adder for Image Processing Applications

Approximate computing (AC) is a recently emerged computing paradigm that can trade in accuracy for power, area, and delay in accuracy-insensitive applications, such as image processing. Magnetic tunnel junction (MTJ) cells can further these AC advancements as a result of their near-zero current leakage. In addition, due to the non-volatility of MTJs, an MTJ-based circuit can switch into a completely OFF state during idle cycles for further power savings without loss of data or the need for extra components. In this article, two novel MTJ-based approximate full-adder circuits are proposed and evaluated. The proposed 1 bit adder circuits are then extended to an 8 bit accuracy-adaptive adder that dynamically adjusts the level of accuracy as needed. For evaluations, we have employed the proposed accuracy-adaptive adder in the implementation of a Gaussian image processing filter. We have observed that, at the expense of a tolerable loss of accuracy, the proposed accuracy-adaptive adder offers up to 47% and 94% improvements in power and performance, respectively, when compared to its conventional accurate counterparts.