Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

M Naga Gowtham Et.Al

doi:10.17762/turcomat.v12i3.1338

Abstract

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Highlights

The adder is one of the most important components of a CPU, ALU, floating-point and address units like cache or memory access unit
Modules 1 and 2 use XNOR module whereas carry module is separately designed to optimize circuit in area of power, delay and chip area as a whole.The XNOR module in this circuit is mostly accountable for the power consumption for the entire adder circuit
The XNOR presented in the project offers low-power, high-speed compared to the six transistors XOR/XNOR.The carry signal obtained at the output for the proposed circuit is implemented as below

Summary

Introduction

The group which has full swing output include CCMOS, CPL, TGA, TFA, Hybrid, 14T, and 16T. Second group full adders comprise of full adders without full swing outputs This full adder has less number of transistors based upon XOR-XNOR, low power consumption, and less area. Different logic styles favour at least one of the performance aspects when compared with each other to design a low power circuit. Mirror adder , another complementary cell do come up with the same results of power consumption and transistor sizing by using the same number of transistors as a conventional CMOS does whereas the maximum propagation path inside the cell is smaller than a conventional CMOS FA circuit.

Methods

Results

Discussion

Conclusion