Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

doi:10.17762/turcomat.v12i5.734

Abstract

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Highlights

The adder is one of the most important components of a CPU, ALU, floating-point and address units like cache or memory access unit
Increased growth in technologies in mobile communication and computing, there has arrived the demand of constructing low power VLSI systems
The main consequence of CPL is voltage degradation which the transmission gate adder successfully addressed without these drawbacks because a Transmission Gate Adder (TGA) uses only 20 transistors to implement a full adder

Summary

Introduction

The group which has full swing output include CCMOS, CPL, TGA, TFA, Hybrid, 14T, and 16T. Second group full adders comprise of full adders without full swing outputs This full adder has less number of transistors based upon XOR-XNOR, low power consumption, and less area. CPL cannot be used in this case of building low power applications/circuitry As such CPL constitutes of high switching activity, more number of transistors, static inverters, more number of inputs are the disadvantages of CPL approach. The main consequence of CPL is voltage degradation which the transmission gate adder successfully addressed without these drawbacks because a TGA uses only 20 transistors to implement a full adder. Later the researchers focused on eliminating all the demerits in each logic style adders by coming up with the hybrid approach to get the better performance of the adder as a whole

Methods

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Discussion

Conclusion