Design of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate and Conventional Static CMOS Logic

Abstract

Since there is a swift technological progress going on in the recent years, semiconductor industry evolved to such an extend that requirement of optimal performance in electronic circuits have become essential. Therefore, there is high requirement of energy efficient fast circuit designs in modern Integrated Circuits (IC). Comparison of two binary digits is one of the fundamental arithmetic operations in Arithmetic Logic Units (ALU) of ICs and processors. A hybrid design approach for implementing a two-bit Magnitude Comparator (MC) has been proposed in this work. The hybrid design consists of three different logic techniques namely: (a) Pass Transistor Logic (PTL), (b) Transmission Gate Logic (TGL) and (c) Conventional Static CMOS Logic (C-CMOS logic). The effectiveness of the proposed design has been compared with 6 state of art two-bit magnitude comparators using Cadence tools in 90 nm technology node. The proposed design showed best perormacne in case of delay and Power Delay Product (PDP) which proved the effectiveness of the design, Moreover, power consumption of the design is also low which makes it highly usable for portable devices that requires low-power consumption.