A New Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Evaluation Trees

Abstract

This chapter proposes a new clocked adiabatic logic (CAL) with complementary pass-transistor logic (CPL) evaluation trees, named as CAL-CPL circuits. The CAL-CPL circuit can be driven by a single-phase power clock. Its energy recovery circuit is the same as CAL circuits, while the evaluation switches consist of CPL blocks. The 1-bit full adder and 5:2 compressors are verified using the proposed CAL-CPL circuits. All circuits are simulated using the Predictive Technology Model (PTM) with 90 nm and 45 nm processes. The proposed CAL-CPL circuits attain large energy savings over a wide range of frequencies, as compared with the conventional static CMOS logic ones.