Revisiting the Utility of Transmission Gate and Passtransistor Logic Styles in CMOS VLSI Design

Abstract

Modern microelectronic circuits are progressing from nanoseconds per instruction to picoseconds per instruction. The miniaturization of transistors, interconnects, and power supplies in integrated circuits have sparked this revolution. Because feature sizes are constantly shrinking, manufacturing process tools have less confidence in controlling design specifications (parameters). To minimize the number of transistors in a particular logic gate, the passtransitor logic can be used at the cost of weak logic output voltages. Transmission gate (TG) logic overcomes the weakness of the passtransistor logic at the expense of an extra transistor for each transmission gate. This study explores the implementation of a two-input OR gate (transmission gate logic), a two-input AND gate (passtransistor logic), and a two-input XOR gate (both) with the simulation results of area, power, and delay metrics.