High performance full subtractor using floating-gate MOSFET

Abstract

Low power consumption has become one of the primary requirements in the design of digital VLSI circuits in recent years. With scaling down of device dimensions, the supply voltage also needs to be scaled down for reliable operation. The speed of conventional digital integrated circuits is degrading on reducing the supply voltage for a given technology. Moreover, the threshold voltage of MOSFET does not scale down proportionally with its dimensions, thus putting a limitation on its suitability for low voltage operation. Therefore, there is a need to explore new methodology for the design of digital circuits well suited for low voltage operation and low power consumption. Floating-gate MOS (FGMOS) technology is one of the design techniques with its attractive features of reduced circuit complexity and threshold voltage programmability. It can be operated below the conventional threshold voltage of MOSFET leading to wider output signal swing at low supply voltage and dissipates less power as compared to CMOS circuits without much compromise on the device performance. This paper presents the design of full subtractor using FGMOS technique whose performance has been compared with full subtractor circuits employing CMOS, transmission gates (TG), complementary pass transistor logic (CPL) and gate diffusion input (GDI). It has been observed that the FGMOS based full subtractor uses minimum number of transistors (10) while consuming least power (1.61×10−9W) with lowest propagation delay (10.62ps) and power delay product (0.17×10−19Js) besides occupying minimum surface area (0.25×10−7cm2) in comparison to CMOS, TG, CPL and GDI based full subtractors available in literature, thus suitable for swift miniaturized applications.