Abstract

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.