An 8-b Multiplier Using Single-Stage Full Adder Cell in Single-Flux-Quantum Circuit Technology

Abstract

Single-flux-quantum (SFQ) circuits operate at higher frequencies with much lower power consumption when compared to their CMOS counterparts. Synchronous SFQ circuits require full path balancing by inserting D-Flipflops as needed, an operation that tends to greatly increase the number of gates in a circuit. To control this increase in the total number of gates, complex multi-input SFQ logic gates can be built and used to synthesize the circuits. In this work, a 1-b full adder is built with sum and carries as two individual single-stage SFQ gates. Both of the sum and the carry cells are demonstrated with their schematics and layouts. Postlayout simulation based on the extracted circuit parameters by InductEx is done by using JSIM and demonstrates the correct functionality of the proposed full adder design. Later, an 8-b signed multiplier using this newly designed single-stage full adder is implemented to illustrate the advantages of the new design. The structure and timing strategy of the multiplier as well as the simulation result are shown. In the end, circuits of different sizes are synthesized with the single-stage full adder circuit, and the results are discussed.