Design of Low-Power and PVT-Aware Quaternary Adder Circuits Based on Virtual Source-CNTFET Model

Abstract

Two new robust quaternary half adder (QHA) circuits (one single source and one multiple sources) are proposed in this work for low power applications. The proposed circuits are designed in hybrid fashion based on three types of quaternary inverter circuits and compared with recently proposed existing models in terms of number of supplies, power dissipation, delay, power-delay product (PDP) and transistor count through extensive simulations in Cadence Virtuoso platform using Stanford’s Virtual Source-Carbon Nanotube Field Effect Transistor (VS-CNTFET) model. The sensitivity of the circuits in response to process parameters, voltage and temperature (PVT) variations are also evaluated. The proposed circuit with multiple sources has the lowest values of 4.92 uW for power consumption and 0.124 fJ for PDP compared to all other designs. Simulation results also demonstrate better stability to PVT variation for both the proposed architectures with respect to power and PDP parameters. In order to evaluate the competency of the proposed QHAs, quaternary full adder (QFA) circuits are designed using the proposed QHAs and other relevant models. Extensive simulation data confirm that the proposed circuits outperform others in terms of power penalty.