Design of Various Low Power and Highspeed Full Adder Designs using 45nm Cmos Technology

Abstract

This project visualizes the different designs of Full Adder (FADDR) circuits. These FADDR circuits are designed mainly to reduce the power and delay factors. If these two factors are minimized then automatically the power delay product (PDP) gets minimized. In addition, to design the FADDR, we used multiplexer. So, that the FADDR transistor count gets reduced. Here in this FADDR implementation, it is designed with different transistors count and the factors like power consumption propagation delay and power delay product (PDP) constraints are tabulated with different transistor count of FADDR designs. Then the power consumption and propagation delay factors get reduced. The designs are simulated by using 45nm CMOS technology in Cadence Virtuoso tool.