Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications

Abstract

Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules. The principal peculiarity of these hybrid logic style-based FA cells is that each module could be optimized individually to improve the circuit performance. A high-performance 1-bit hybrid FA cell is proposed with pass transistor logic and transmission gate logic in the present work. The proposed FA circuit is implemented using 20-transistors to achieve optimum performance. The proposed circuit is simulated in Cadence virtuoso tool by using 90-nm process CMOS technology. Comparison of the design matrices for the proposed 1-bit hybrid FA cell against the five different reported FA circuits is also carried out. The present study reported 13.01–54.93 % and 13.01–59.20 % improvement in terms of delay and power delay product (PDP), respectively, compared to other FA designs. The proposed circuit is also investigated in different supply voltages (0.6–1.5V). Furthermore, the FA circuit is verified in different process corner conditions to check the robustness.